2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献

Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology 基于0.13 μm SiGe BiCMOS技术的高性能e波段SPDT开关和LNA设计

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-24 DOI: 10.1109/NORCHIP.2017.8124975

Raju Ahamed, M. Varonen, D. Parveg, J. Saijets, K. Halonen

{"title":"Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology","authors":"Raju Ahamed, M. Varonen, D. Parveg, J. Saijets, K. Halonen","doi":"10.1109/NORCHIP.2017.8124975","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124975","url":null,"abstract":"This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127462829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Ring-oscillator-based timing generator for ultralow-power applications 用于超低功耗应用的基于环形振荡器的定时发生器

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124969

Pavel Angelov, Martin Nielsen-Lönn, A. Alvandpour

{"title":"Ring-oscillator-based timing generator for ultralow-power applications","authors":"Pavel Angelov, Martin Nielsen-Lönn, A. Alvandpour","doi":"10.1109/NORCHIP.2017.8124969","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124969","url":null,"abstract":"Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"393 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A capacitance multiplier based on DBTA 基于DBTA的电容倍增器

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124988

J. Vavra

引用次数: 7

The effect of DPD bandwidth limitation on EVM for a 28 nm WLAN 802.11ac transmitter DPD带宽限制对28nm WLAN 802.11ac发射机EVM的影响

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124943

Oscar Morales Chacon, T. Johansson, Thomas Flink

引用次数: 0

Can real-time systems benefit from dynamic partial reconfiguration? 实时系统能从动态部分重构中获益吗?

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124984

Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, J. Sparsø

{"title":"Can real-time systems benefit from dynamic partial reconfiguration?","authors":"Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, J. Sparsø","doi":"10.1109/NORCHIP.2017.8124984","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124984","url":null,"abstract":"In real-time systems, a solution where hardware accelerators are used to implement computationally intensive tasks can be easier to analyze, in terms of worst-case execution time (WCET), than a pure software solution. However, when using FPGAs, the amount and the complexity of the hardware accelerators are limited by the resources available. Dynamic partial reconfiguration (DPR) of FPGAs can be used to overcome this limitation by replacing the accelerators that are only required for limited amounts of time with new ones. This paper investigates the potential benefits of using DPR to implement hardware accelerators in real-time systems and presents an experimental analysis of the trade-offs between hardware utilization and WCET increase due to the reconfiguration time overhead of DPR. We also investigate the trade-off between the use of multiple specialized accelerators combined with DPR instead of the use of a more general accelerator. The results show that, for computationally intensive tasks, the use of DPR can lead to a more efficient use of the FPGA, while maintaining comparable computational performance.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127978768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

High-level synthesis for reduction of WCET in real-time systems 实时系统中降低WCET的高级综合

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124945

Andreas Toftegaard Kristensen, Luca Pezzarossa, J. Sparsø

{"title":"High-level synthesis for reduction of WCET in real-time systems","authors":"Andreas Toftegaard Kristensen, Luca Pezzarossa, J. Sparsø","doi":"10.1109/NORCHIP.2017.8124945","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124945","url":null,"abstract":"The increasing design complexity of systems-on-chip (SoCs) requires designers to work at higher levels of abstraction. High-level synthesis (HLS) is one approach towards this. It allows designers to synthesize hardware directly from code written in a high-level programming language and to more quickly explore alternative implementations by re-running the synthesis with different optimization parameters and pragmas. HLS is particularly interesting for FPGA circuits, where different hardware implementations can easily be loaded into the target device. Another perspective on HLS is performance. Compared to executing the high-level language code on a processor, HLS can be used to create hardware that accelerates critical parts of the code. When discussing performance in the context or real-time systems, it is the worst-case execution time (WCET) of a task that matters. WCET obviously benefits from hardware acceleration, but it may also benefit from a tighter bound on the WCET. This paper explores the use of and integration of accelerators generated using HLS into a time-predictable processor intended for real-time systems. The high-level design tool, Vivado HLS, is used to generate hardware accelerators from benchmark code, and the system using the generated hardware accelerators is evaluated against the WCET of the original code. The design evaluation is carried out using the Patmos processor from the open-source T-CREST platform and implemented on a Xilinx Artix 7 FPGA. The WCET speed-up achieved is between a factor of 5 and 70.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130907859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Zero-crossing detector for a piezoelectric energy harvester 压电能量采集器的过零检测器

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124957

Franz Marcus Schüffny, Michael Hayoz, Cheolyong Bae, I. Arya, M. Gokhale, Annapragada Hema Chandar, Martin Nielsen-Lönn, Pavel Angelov

引用次数: 2

Active charge pumping power-saving technique for SC integrators SC集成商主动电荷泵送节能技术

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124985

Jia Sun, T. Rahkonen

引用次数: 0

Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller 使用EDAC SDRAM控制器减轻COTS SDRAM中的单事件干扰

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124978

Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg

{"title":"Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller","authors":"Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg","doi":"10.1109/NORCHIP.2017.8124978","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124978","url":null,"abstract":"From deep space missions to low-earth orbit satellites, the natural radiation of space proves to be a hostile environment for electronics. Memory elements in particular are highly susceptible to radiation charge that if latched can cause single-event upsets (SEU, bit-flips) which lead to data corruption and even mission critical failures. On Earth, SDRAM devices are widely used as a cost-effective, high performance storage elements in almost every computer system. However, their physical design makes them highly susceptible to SEUs. Thus, their usage in space application is limited and usually avoided, requiring the use of radiation hardened components which are generally a few generations older and often much more expensive than COTS. In this paper, an off-chip SEU/MBU mitigation mechanism is presented that aims to drastically reduce the probability of data corruption inside a commercial-off-the-shelf (COTS) synchronous dynamic random access memory (SDRAM) using a triple modular redundant (TMR) scheme for data and periodic scrubbing. The proposed mitigation technique is implemented in a novel controller that will be used by the single-event upset detector (SEUD) experiment aboard the KTH MInature STudent (MIST) satellite project.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

ESD induced EMS problems in digital IOs 电子IOs中ESD引起的EMS问题

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124971

T. Ostermann

引用次数: 3