基于0.13 μm SiGe BiCMOS技术的高性能e波段SPDT开关和LNA设计

Raju Ahamed, M. Varonen, D. Parveg, J. Saijets, K. Halonen
{"title":"基于0.13 μm SiGe BiCMOS技术的高性能e波段SPDT开关和LNA设计","authors":"Raju Ahamed, M. Varonen, D. Parveg, J. Saijets, K. Halonen","doi":"10.1109/NORCHIP.2017.8124975","DOIUrl":null,"url":null,"abstract":"This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology\",\"authors\":\"Raju Ahamed, M. Varonen, D. Parveg, J. Saijets, K. Halonen\",\"doi\":\"10.1109/NORCHIP.2017.8124975\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.\",\"PeriodicalId\":373686,\"journal\":{\"name\":\"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHIP.2017.8124975\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2017.8124975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种基于0.13 μm SiGe BiCMOS技术的高性能e波段单极双通(SPDT)开关和低噪声放大器(LNA)作为收发器前端的设计方案。四分之一波并联SPDT开关采用反饱和SiGe hbt设计。该开关的插入损耗为2.1 dB,隔离度为26 dB,反射系数在75 GHz时优于18 dB,带宽超过35 GHz。所设计的开关集成了一个单路差分输出(SIDO)低噪声放大器(LNA),并用作LNA的输入匹配元件。LNA在第一级使用共发射极放大器,在第二级使用反级码放大器,以利用共发射极和反级码拓扑的优点。所得到的带集成开关的LNA在75 GHz时的增益和噪声系数(NF)分别为26 dB和6.9 dB,带宽为12 GHz的3 dB。在75 GHz时达到+5.5 dBm的输出参考1 db压缩点。该集成模块的直流功耗为45.5 mW,不包括射频垫,其面积为720 μm × 580 μm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology
This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信