Sina Shahhosseini, Kasra Moazzemi, A. Rahmani, N. Dutt
{"title":"Dependability evaluation of SISO control-theoretic power managers for processor architectures","authors":"Sina Shahhosseini, Kasra Moazzemi, A. Rahmani, N. Dutt","doi":"10.1109/NORCHIP.2017.8124983","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124983","url":null,"abstract":"Dynamic power managers are increasingly being deployed in modern embedded processors to meet performance/power requirements of new workloads. These computing systems are limited in their power dissipation, demanding a dependable power management scheme to guarantee the system's efficiency and dependability. Although several ad-hoc and heuristic power management approaches can be found in the literature, their main shortcoming is the lack of formal guarantees to ensure dependability of the processors. Control-theoretic approaches promise flexibility and robustness for power management strategies. However, the creation of a responsive yet stable controller requires the often neglected tasks of proper system identification and performance analysis for target applications. This paper presents dependability evaluation of Single-Input Single-Output (SISO) for power management on processor architectures. We also analyze the effect of frequent application phase changes on the responsiveness of controllers. We evaluate responsiveness of different class of applications to computer system control inputs such as DVFS. We illustrate the feasibility of hardware and software SISO controllers for power management using the Sniper simulator running SPLASH2 and microbenchmarks. Based on our observations, we provide guidelines for developing stable and robust SISO controllers for power management, show the scenarios where simple classic SISO controllers might not be effective, and identify early symptoms that may result in instability for power management controllers.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"1098 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Maya Matsunaga, T. Nakanishi, A. Kobayashi, K. Nakazato, K. Niitsu
{"title":"Three-dimensional millimeter-wave frequency-shift-based CMOS biosensor using vertically stacked LC oscillators","authors":"Maya Matsunaga, T. Nakanishi, A. Kobayashi, K. Nakazato, K. Niitsu","doi":"10.1109/NORCHIP.2017.8124974","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124974","url":null,"abstract":"This paper proposes a novel millimeter-wave frequency-shift-based CMOS biosensor capable of providing three-dimensional (3D) resolution. Using vertically stacked LC oscillators, the vertical resolution from the sensor chip surface can be obtained, which enables 3D target detection. Since the shifts in the frequencies of the upper and lower LC oscillators are different because of the changes in the complex dielectric constant of the target, the target can be detected in 3D. To verify the effectiveness of the proposed approach, a test chip was fabricated using a 65 nm CMOS process. The measurement results showed differences in the resonance frequency shifts of the upper and lower LC oscillators, which highlighted the capability of the proposed biosensor to provide 3D resolution.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Ostrovsky, K. Tittelbach-Helmrich, F. Herzel, O. Schrape, G. Fischer, D. Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh
{"title":"A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology","authors":"P. Ostrovsky, K. Tittelbach-Helmrich, F. Herzel, O. Schrape, G. Fischer, D. Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh","doi":"10.1109/NORCHIP.2017.8124990","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124990","url":null,"abstract":"This paper presents design considerations and measurements of a dual channel 16 GSps single chip arbitrary waveform generator. Each generator channel consists of a 1.6 Mbit SRAM block, a multiplexing chain, and a 4-bit DAC. A low phase noise 16 GHz PLL is integrated on the same chip. The prototype is designed to perform a lab experiment of a real-time SAW spectrometer. The overall power consumption of the chip is 1.45 W.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131309814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-resolution reconfigurable sigma-delta Digital-to-Analog Converter for RF pulse transmission in MRI scanners","authors":"S. Qazi, Syed Asmat Ali Shah, H. Omer, J. Wikner","doi":"10.1109/NORCHIP.2017.8124973","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124973","url":null,"abstract":"In Magnetic Resonance Imaging (MRI) scanners Radio Frequency (RF) signals are important to accurately excite target tissues. RF signals depend on Digital-to-Analog Converter's (DAC) output which depends on sequence numbers issued from control room. This paper presents a sigma-delta modulator (SDM), followed by a DAC architecture that can be reconfigured while an MRI scanner is operating and pipelining is not required. The reconfigurable SDM is implemented in a 65nm CMOS technology and operates at an oversampling ratio (OSR) of 64 times. The modulator clocks at 2 GHz frequency with a 1.2-V supply voltage. The modulator occupies an area of 29 × 32 sq μm and consumes 319.1 mW. The proposed SDM-DAC is well-suited for the RF transmitter in the MRI scanner. The reconfigurability feature allows to select different resolutions for various types of RF pulses and can thereby target specific tissues more accurately. 1","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133952947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeppe Gaardsted Davidsen, Yoni Yosef-Hay, D. Larsen, I. Jørgensen
{"title":"Synthesis and design of a fully integrated multi-topology switched capacitor DC-DC converter with gearbox control","authors":"Jeppe Gaardsted Davidsen, Yoni Yosef-Hay, D. Larsen, I. Jørgensen","doi":"10.1109/NORCHIP.2017.8124994","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124994","url":null,"abstract":"This paper discusses a methodology of minimizing the amount of switches in a multi-topology fully integrated switched capacitor dc-dc converter powered by a super capacitor for energy harvesting purposes. The design of a simple controlling circuit for the multi-topology power stage using a gearbox approach is presented with all the required circuits. The converter is able to generate a output voltage of 1.2 V from a 470 mF capacitor charged to 3 V down to 1.4 V. The output voltage is regulated with a ripple voltage below 7 mV. The controlling circuit including buffers with ideal comparators has a power consumption of 129 μW, the average efficiency is 67% and the peak efficiency of the converter is 81%.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122503646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving microarchitecture design and hardware generation using micro-language IP cores","authors":"Alexander P. Antonov, P. Kustarev, S. Bikovsky","doi":"10.1109/NORCHIP.2017.8124952","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124952","url":null,"abstract":"The need of rapid design space exploration, early prototype construction and high level of reuse of technical decisions about microarchitecture in hardware design field actualize development of technologies based on custom user-specified hardware generation. However, existing approaches and tools typically offer configurability at the level of predefined set of parameters. In the article, the concept of framework architecture based on Micro-Language IP (MLIP) cores is presented. This approach facilitates creation of lightweight hardware description languages adapted to specific microarchitectural patterns. Furthermore, prototype implementation of the framework is described, followed by description of two experimental MLIP cores, rtl and pipe. These cores provide domain-specific languages for procedural generation of general-purpose RTL and pipelined hardware structures respectively. The developed means have been utilized for rapid designing of educational CPU core that has proved its operational capability in FPGA. We envision complementation of procedural hardware generation approach with microarchitecture-specific DSLs to be promising for raising the level of abstraction in microarchitecture design. This can reduce design duration of complex hardware units by up to two times, assuming either usage of common microarchitectural patterns or embodying of original ones in the new MLIP cores as an integral part of hardware design process.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124434935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bhavin Odedara, S. Bojja, Nitin Gupta, I. Rapoport, Tony Ross, Alik Zelichenok
{"title":"A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process","authors":"Bhavin Odedara, S. Bojja, Nitin Gupta, I. Rapoport, Tony Ross, Alik Zelichenok","doi":"10.1109/NORCHIP.2017.8124955","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124955","url":null,"abstract":"Systems-On-Chip (SOC) solutions for flash memory controllers often require multiple clocks with different frequencies for various sub-systems to achieve optimal performance. Traditionally this is achieved by multiple oscillators (RC or LC based) or Phase-Locked-Loops (PLLs) or Multiplying-Delay-Locked-Loops (MDLLs). Another popular approach is a single PLL with multiple open-loop fractional-dividers. In this paper, we propose an area and power efficient scheme to generate multiple clocks at different frequencies using a single PLL loop with multiple Voltage-Controlled-Oscillators (VCOs). The solution also offers higher supply noise immunity. Moreover, control logic is in-built to make multiple frequency outputs programmable to allow SOC performance optimization depending on Process, Voltage and Temperature. The circuit is designed in a standard 28nm CMOS technology and works with 0.9V digital supply.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126314063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. A. Shaheen, Rehman Akbar, Alok Sethi, J. Aikio, T. Rahkonen, A. Pärssinen
{"title":"A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5G","authors":"R. A. Shaheen, Rehman Akbar, Alok Sethi, J. Aikio, T. Rahkonen, A. Pärssinen","doi":"10.1109/NORCHIP.2017.8124989","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124989","url":null,"abstract":"A four element, two channel Multiple-Input Multiple-Output (MIMO) phased array receiver at 15 GHz is designed and fabricated in 45nm CMOS SOI process. The receiver consists of two independent four-antenna phasedarrays for hybrid beamforming and MIMO processing in digital domain. Phase and amplitude control is based on RF IQ vector modulator (VM) at carrier frequency. Measured downconversion gain and noise figure (NF) of one path are 23 dB and 5.4dB, respectively, giving estimated 3.4 dB NF for the IC when simulated PCB and matching losses are taken into account. 1 dB compression and IIP3 points are −37 dBm and −28 dBm, respectively. One phased array consumes 486 mW DC power from 1.2V power supply. Total chip area is 5.69 mm2.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126322434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Workload prediction for runtime resource management","authors":"Mina Niknafs, I. Ukhov, P. Eles, Zebo Peng","doi":"10.1109/NORCHIP.2017.8124965","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124965","url":null,"abstract":"An intelligent resource manager is an essential part of platforms based on heterogeneous architectures. The resource manager should be able to accurately predict the future workload of the system at hand and take it into consideration for making decisions. In this paper, we study a large computer cluster and show that there exist patterns in the sequence of applications that each user runs over time, and that these patterns can be used for modeling and prediction of the applications that will be requested in the future. To this end, we develop a predictive technique based on the n-gram model. It is shown that, due to the varied nature of application sequences of different users, a universal model does not provide optimal results, and a customized model should be constructed for each user. The experimental results show that the straightforward methods have a prediction accuracy below 16% when assessed on a real-life data set. Our technique provides an accuracy improvement of more than 51% in comparison with the straightforward method.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127004256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}