2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献_第2页

Towards software performance estimation based on register-transfer level descriptions 基于寄存器传输级描述的软件性能评估

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124967

H. Puttnies, Christoph Niemann, Sascha Rohde, D. Timmermann, J. Schacht

{"title":"Towards software performance estimation based on register-transfer level descriptions","authors":"H. Puttnies, Christoph Niemann, Sascha Rohde, D. Timmermann, J. Schacht","doi":"10.1109/NORCHIP.2017.8124967","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124967","url":null,"abstract":"The concept of hardware-software codesign allows to cope with the increasing complexity of very large scale integration (VLSI) systems. This concept is based on design space exploration (DSE), which means the systematic altering of design parameters (e.g., parallelization, serialisation, implementation of a functionality in software or hardware) to improve the final design. Existing DSE approaches work with high-level descriptions (e.g., SystemC) of the functionality. However, if existing systems (or submodules of those) shall be reused, only a synthesizable register-transfer level (RTL) description of these functionalities is necessarily given. Consequently, the RTL modules cannot be considered during the DSE. We propose an approach to this problem of reasonable practical relevance. To conduct the DSE, we estimate the software execution time of a functionality based on its RTL description. We show in an evaluation that this estimation is possible based on RTL code. In addition, we propose several suggestions to mitigate the problem that the software execution time of a functionality is highly dependent on the input data, which are often unknown at design time.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A dependable ASIC architecture with RT-level rollback for controller soft error recovery 具有rt级回滚的可靠ASIC架构，用于控制器软错误恢复

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124986

Keisuke Inoue

引用次数: 0

A self-consistent Carleman linearization approach for the design of RF mixer circuits 一种用于射频混频器电路设计的自洽卡尔曼线性化方法

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124950

Harry Weber, Gerald Alexander Koroa, W. Mathis, D. Delchev, G. Marinova

引用次数: 1

An RNS based modular multiplier with reduced complexity 基于RNS的模块化乘法器，降低了复杂度

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124953

Shahzad Asif, M. Vesterbacka

引用次数: 1

Subsampling phase-locked loop behavioural modelling approach for phase noise evaluation 相位噪声评价的子采样锁相环行为建模方法

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124991

Peco Gjurovski, M. Wei, R. Negra

引用次数: 0

Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs fpga上容错、全局异步、局部同步、芯片间NoC通信桥的实现

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124972

Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg

{"title":"Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs","authors":"Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg","doi":"10.1109/NORCHIP.2017.8124972","DOIUrl":"https://doi.org/10.1109/NORCHIP.2017.8124972","url":null,"abstract":"Network-on-Chip (NoC) architectures were introduced to help mitigate the bottleneck and scalability issues faced by the traditional bus interconnect in Multi-Processor System-On Chip (MPSoC). Nowadays, many embedded systems host a significant number of micro-controllers and processors (i.e. vehicles, airplanes, satellites, etc.) and as this number continues to increase, traditional bus solutions will start to fail on those platforms as well. NoCs not only offer a scalable solution for MPSoC interconnects but they can also provide a uniform platform of communication to embedded systems with multiple off-chip, often heterogeneous, processors. This leads to the need for investigation on inter-chip communication bridges suitable for transmitting flits/packets across chips and possibly across clock domains. This paper investigates an inter-chip communication link, of an MPSoC NoC architecture which is extended with an off-chip, heterogeneous processor (node) and proposes a scalable, fault-tolerant, globally asynchronous locally synchronous bridge for inter-chip communication. The proposed bridge is implemented on a prototype board of the SEUD KTH experiment where it successfully enables the communication of a NoC distributed over two FPGAs. The inter-chip bridge is verified in-circuit achieving transfer speeds up to 24 MByte/s (≈ 1.5 Mflit/s) and its ability to correct single bit errors is demonstrated in simulation.","PeriodicalId":373686,"journal":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A highly compact, 16.8 dBm Pgat Ka-band power amplifier in 250 nm SiGe:C BiCMOS 高度紧凑，16.8 dBm pga ka波段功率放大器在250纳米SiGe:C BiCMOS

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124959

Iancu Somesanu, H. Schumacher

引用次数: 7

Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses 突触后反应的大范围时间模式的节能神经形态受体

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124951

Xuefei You, A. Zjajo, Sumeet S. Kumar, R. V. Leuken

引用次数: 2

Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory 嵌入式低电压NOR快闪存储器中电荷泵的功率效率优化

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124949

W. SteveNgueya, Julien Mellier, Stephane Ricard, J. Portal, H. Aziza

引用次数: 2

Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting 用于能量收集的自振荡多电平开关电容DC/DC变换器

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2017-10-01 DOI: 10.1109/NORCHIP.2017.8124977

Martin Nielsen-Lönn, Pavel Angelov, J. Wikner, A. Alvandpour

引用次数: 3