2010 VI Southern Programmable Logic Conference (SPL)最新文献

A flexible implementation of a matrix Laurent series-based 16-point fast Fourier and Hartley transforms 一个基于洛朗级数的矩阵的灵活实现，16点快速傅里叶和哈特利变换

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2015-02-20 DOI: 10.1109/SPL.2010.5483017

R. Oliveira, Hélio M. de Oliveira, R. Souza, E. J. P. Santos

引用次数: 2

FPGA based floating-point library for CORDIC algorithms 基于FPGA的CORDIC算法浮点库

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483002

D. Muñoz, Diego F. Sánchez, C. Llanos, M. Ayala-Rincón

{"title":"FPGA based floating-point library for CORDIC algorithms","authors":"D. Muñoz, Diego F. Sánchez, C. Llanos, M. Ayala-Rincón","doi":"10.1109/SPL.2010.5483002","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483002","url":null,"abstract":"Computation of floating-point transcendental functions has a relevant importance in a wide variety of scientific applications, where the area cost, error and latency are important requirements to be attended. This paper describes a flexible FPGA implementation of a parameterizable floating-point library for computing sine, cosine, arctangent and exponential functions using the CORDIC algorithm. The novelty of the proposed architecture is that by sharing the same resources the CORDIC algorithm can be used in two operation modes, allowing it to compute the sine, cosine or arctangent functions. Additionally, in case of the exponential function, the architectures change automatically between the CORDIC or a Taylor approach, which helps to improve the precision characteristics of the circuit, specifically for small input values after the argument reduction. Synthesis of the circuits and an experimental analysis of the errors have demonstrated the correctness and effectiveness of the implemented cores and allow the designer to choose, for general-purpose applications, a suitable bit-width representation and number of iterations of the CORDIC algorithm.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126674183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Delay modeling for power noise-aware design in Spartan-3A FPGAs Spartan-3A fpga中功率噪声感知设计的延迟建模

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483026

J. Freijedo, M. Valdés, M. J. Moure, L. Costas, J. Rodríguez-Andina, J. Semião, F. Vargas, I. Teixeira, J. P. Teixeira

引用次数: 0

A general-purpose dynamically reconfigurable SVM 一种通用的动态可重构SVM

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483031

J. Gomes Filho, M. Raffo, M. Strum, W. Chau

引用次数: 12

Protection of microprocessor-based cores for FPL devices FPL器件中基于微处理器内核的保护

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483008

L. Parrilla, Encarnación Castillo, Antonio García, D. González, A. Lloris, E. Todorovich, E. Boemo

引用次数: 1

Design and implementation of packet switching capabilities on 10GbE MAC core 10GbE MAC核上分组交换功能的设计与实现

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483024

Roman Arenas, J. Finochietto, Leonardo M Rocha

引用次数: 0

A placement tool for a NOC-based dynamically reconfigurable system 一个用于基于noc的动态可重构系统的放置工具

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483005

M. Raffo, J. Gomes Filho, M. Strum, W. Chau

引用次数: 7

Parallel decimal multipliers using binary multipliers 使用二进制乘数的并行十进制乘数

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483001

M. Véstias, H. Neto

引用次数: 36

A Genetic Programming based approach for efficiently exploring architectural communication design space of MPSoCs 基于遗传规划的mpsoc架构通信设计空间有效探索方法

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483006

Guilherme Esmeraldo, E. Barros

{"title":"A Genetic Programming based approach for efficiently exploring architectural communication design space of MPSoCs","authors":"Guilherme Esmeraldo, E. Barros","doi":"10.1109/SPL.2010.5483006","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483006","url":null,"abstract":"New integrated circuits technologies and the demand for more complex applications have created Multi-Processor System-on-Chip (MPSoC). MPSoC is a complex integrated circuit, which can be composed of microprocessors, buses, memories and others computational system components. As the number and variety of components of today's MPSoC is increasing, its communication architecture is becoming a limiting factor for applications performance and power consumption. Thus, techniques have been created for exploring the design space in order to find out the best communication architecture for a given application. Such techniques, however, are either inaccurate (by using static analysis based approaches) or very time consuming since each communication configuration of the design space must be simulated (by using simulation models) or estimated (using mixed approaches). This paper presents a new approach to explore the design space of bus-based communication architectures of MPSoCs using Generalized Linear Models and Genetic Programming. By using the proposed approach, some experiments show that it was possible to explore a subset of the design space and to identify the best communication configuration for a given application reducing 90% of the exploration time with less of 3,8% mean global error.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127774962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Decimal division: Algorithms and FPGA implementations 十进制除法:算法和FPGA实现

2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483000

J. Deschamps, G. Sutter

引用次数: 14