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An environment for energy consumption analysis of cache memories in SoC platforms SoC平台中高速缓存存储器的能耗分析环境
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483007
F. Cordeiro, A. Silva-Filho, C. Araujo, M. Gomes, Edenia N. Barros, M. E. Lima
{"title":"An environment for energy consumption analysis of cache memories in SoC platforms","authors":"F. Cordeiro, A. Silva-Filho, C. Araujo, M. Gomes, Edenia N. Barros, M. E. Lima","doi":"10.1109/SPL.2010.5483007","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483007","url":null,"abstract":"The tuning of cache architectures in platforms for embedded systems applications can dramatically reduce energy consumption. The existing cache exploration environments constrain the designer to analyze cache energy consumption on single processor systems and worse, systems that are based on a single processor type. In this paper is presented the PCacheEnergyAnalyzer environment for energy consumption analysis of cache memory on SoC platforms. This is a powerful energy analysis environment that combines the use of efficient tools to provide static and dynamic energy consumption analysis, the flexibility to support the architecture exploration of cache memories on platforms that are not bound to a specific processor, and fast simulation techniques. The proposed environment has been integrated into the SoC modeling framework PDesigner, providing a user-friendly graphical interface allowing the integrated modeling and cache energy analysis of SoCs. The PCacheEnergyAnalyzer has been validated with four applications of the Mediabench suite benchmark.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The supersmall soft processor 超小型软处理器
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483016
James Robinson, Samira Vafaee, John Scobbie, M. Ritche, Jonathan Rose
{"title":"The supersmall soft processor","authors":"James Robinson, Samira Vafaee, John Scobbie, M. Ritche, Jonathan Rose","doi":"10.1109/SPL.2010.5483016","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483016","url":null,"abstract":"Soft processors have become an increasingly common component of systems that use Field-Programmable Gate Arrays (FPGAs), and are used to implement a wide variety of control and data processing functionality. Often, some additional functionality needs to be added to a system when there is very little space left on the physical device. This functionality may not be performance critical, and so could be implemented on a slow soft processor. For this reason it may be useful to have a processor that is as small as possible yet similar to other commonly-used processors. This paper describes the design, implementation and release of a 32-bit soft processor based on the MIPS-I instruction set and optimized for minimal use of FPGA resources. The ‘supersmall’ soft processor is as much as 2.2 times smaller than Altera's Nios II/e (the smallest of their 3 processors) yet only a factor of 10 times slower.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126249477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
FPGA-based real time processing of the plenoptic wavefront sensor for the european solar telescope (EST) 基于fpga的欧洲太阳望远镜全光波前传感器实时处理
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483032
Y. Martín, L. Rodríguez-Ramos, J. Garcia, J. J. Díaz García, J. Rodríguez-Ramos
{"title":"FPGA-based real time processing of the plenoptic wavefront sensor for the european solar telescope (EST)","authors":"Y. Martín, L. Rodríguez-Ramos, J. Garcia, J. J. Díaz García, J. Rodríguez-Ramos","doi":"10.1109/SPL.2010.5483032","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483032","url":null,"abstract":"This paper describes the development of the plenoptic wave front sensor for an adaptive optics systems proposed for the future EST Solar telescope. The plenoptic sensor offers additional optical information compared to traditional sensors at the expense of a significant increase in the image processing. This paper will concentrate on the processing required to develop a viable plenoptic sensor, describing the algorithm and the real time implementation in FPGAs (Field Programmable Gate Arrays). The aim of this work is to demonstrate that by using the advantages of the FPGAs in terms of parallel processing, speed and cost figures the plenoptic sensor real-time processing is perfectly viable. Consequently, the proposed system appears as a competitive alternative for the traditional wave front sensors systems.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"44 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Libor market model simulation on an FPGA parallel machine 基于FPGA并行机的Libor市场模型仿真
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483011
Xiang Tian, K. Benkrid
{"title":"Libor market model simulation on an FPGA parallel machine","authors":"Xiang Tian, K. Benkrid","doi":"10.1109/SPL.2010.5483011","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483011","url":null,"abstract":"In this paper, we present a high performance scalable FPGA design and implementation of an interest rate derivative pricing engine that targets on the cap pricing. The design consists of a Gaussian random number generator, based on the Mersenne Twister uniform random generator, and a Monte Carlo path generation engine which calculates the prices of an interest rate derivative based on the LIBOR market model. We implemented this design on the Maxwell FPGA supercomputer using up to 32 Xilinx XC4VFX100 FPGA nodes. We have also compared our FPGA hardware implementation with an equivalent optimized pure software implementation running on up to 32 2.8GHz Xeon processors with 1 GB RAM each. This showed our FPGA implementation to be 58x faster than the optimized software implementation, while being more than two orders of magnitude more energy efficient. These results scale linearly with the number of FPGA and Xeon processor nodes used.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132195165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The development of a hardware abstraction layer generator for system-on-chip functional verification 开发了一种用于片上系统功能验证的硬件抽象层生成器
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483004
T. Lins, E. Barros
{"title":"The development of a hardware abstraction layer generator for system-on-chip functional verification","authors":"T. Lins, E. Barros","doi":"10.1109/SPL.2010.5483004","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483004","url":null,"abstract":"Nowadays functional verification of large system-on-chip has taken about 70% to 80% of the total design effort. The large amount of IP's of current SoC's makes the work of verification engineers quite hard due to the need to guarantee that the design is bug free before it is sent to tape out. In order to reduce the time spent in the functional verification and support the verification engineers, this work proposes a Hardware Abstract Layer (HAL) generator. The HAL generator is part of a methodology for SoC functional verification, which is supported by IP-XACT and aims to automate the functional verification flow. The HAL generator is able for creating C functions that allow the manipulation of registers and their fields at a very high abstraction level allowing the verification engineers to write their test cases without need to worrying about masks, macros, define and/or pointers manipulation.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133385639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implementation of a SigmaBoost-based ensemble of SVM in a multiple processor system on chip 基于sigmaboost的支持向量机集成在片上多处理器系统中的实现
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483014
D. C. Lopes, N. H. C. Lima, J.D. de Melo, A. Neto
{"title":"Implementation of a SigmaBoost-based ensemble of SVM in a multiple processor system on chip","authors":"D. C. Lopes, N. H. C. Lima, J.D. de Melo, A. Neto","doi":"10.1109/SPL.2010.5483014","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483014","url":null,"abstract":"This paper shows the effectiveness of a classifier ensemble composed of weak classifiers trained with a boosting algorithm implemented in a multiprocessor system on chip. The network is applied on the classification on thyroid disease diagnosis. The objective is to show that, even an FPGA with hardware restrictions, can be used to implement a complex problem, when parallel processing is used. To improve the system performance four soft processors were used with a shared memory.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimized label-broadcast parallel algorithm for connected components labeling 一种优化的标记广播并行算法用于连接元件的标记
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483030
J. M. Teixeira, Bernardo Reis, V. Teichrieb, J. Kelner
{"title":"An optimized label-broadcast parallel algorithm for connected components labeling","authors":"J. M. Teixeira, Bernardo Reis, V. Teichrieb, J. Kelner","doi":"10.1109/SPL.2010.5483030","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483030","url":null,"abstract":"This paper presents a simple and fast algorithm for labeling connected components in binary images, based on a parallel label-broadcast paradigm. A grid of processing units (called spiders) is used and each element is responsible for updating its label value, during a specific number of iterations. We describe the design and implementation of an embedded architecture for real-time labeling of black and white images based on FPGA technology. Since the image is divided and processed independently by processing elements, it is possible to use the proposed algorithm in an FPGA platform attached to an image sensor and have a focal plane processor circuit-like.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"22 14_suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128187736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A full duplex implementation of Internet Protocol version 4 in an FPGA device Internet协议版本4在FPGA器件中的全双工实现
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483020
P. D. de Aguirre, Lucas Teixeira, C. Müller, F. Herrmann, Leandro Z Pieper, Josué de Freitas, G. Dessbesell, J. B. Martins
{"title":"A full duplex implementation of Internet Protocol version 4 in an FPGA device","authors":"P. D. de Aguirre, Lucas Teixeira, C. Müller, F. Herrmann, Leandro Z Pieper, Josué de Freitas, G. Dessbesell, J. B. Martins","doi":"10.1109/SPL.2010.5483020","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483020","url":null,"abstract":"This paper describes an implementation in hardware of Internet Protocol version 4. Routing and addressing features were integrated with Network Interfaces and synthesized to a Stratix II FPGA device. Our work showed two implementations of a full duplex Internet Protocol version 4. The first implementation consists in a Reference design and the second uses the same design but with more buffer space. We present the advantages and disadvantages of each implementation and also compare in terms of throughput, frame loss rate and power dissipation. The implementation with more buffer space presents a better performance in frame loss rate but it dissipates more power than the Reference design. Both implementations presented similar results for throughput tests.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114144781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections 基于FPGA的多TCP连接状态检测复杂规则匹配体系结构
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483029
C. Greco, Enrico Nobile, S. Pontarelli, S. Teofili
{"title":"An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections","authors":"C. Greco, Enrico Nobile, S. Pontarelli, S. Teofili","doi":"10.1109/SPL.2010.5483029","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483029","url":null,"abstract":"In this paper a novel architecture for string matching is presented. It is oriented to an FPGA implementation and, differently from other similar works, it is particularly suitable for rules matching in multiple streams. The paper presents our developed architecture able to efficiently manage different streams, discusses how to optimize the design to limit the number of FPGA logic resources and shows the obtained results.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardware design for fast intermode decision and for residues generaton in a variable block size motion estimation compliant with the H.264/AVC video coding standard 硬件设计符合H.264/AVC视频编码标准，用于快速模间决策和可变块大小运动估计中的残数生成
2010 VI Southern Programmable Logic Conference (SPL) Pub Date : 2010-03-24 DOI: 10.1109/SPL.2010.5483015
R. Porto, S. Bampi, L. Agostini
{"title":"Hardware design for fast intermode decision and for residues generaton in a variable block size motion estimation compliant with the H.264/AVC video coding standard","authors":"R. Porto, S. Bampi, L. Agostini","doi":"10.1109/SPL.2010.5483015","DOIUrl":"https://doi.org/10.1109/SPL.2010.5483015","url":null,"abstract":"H.264/AVC is the latest video coding standard. It reaches the highest compression rates when compared to previous standards. On the other hand, it has a high computational complexity mainly due to motion estimation and its mode decision. Considering the high number of calculations, hardware implementations become essential. Moreover, it is important try to find alternatives to simplify the H.264/AVC mode decision. Another desirable improvement is an efficient way to provide the residual blocks of motion estimation to the next encoding steps. Addressing hardware architectures, this work presents an architecture for fast inter mode decision and production of residual blocks. The variable block-size motion estimation architecture used is based on full search algorithm, SAD calculation, and it produces the 41 motion vectors within a macroblock. The architectures were described in VHDL and mapped to a Xilinx FPGA. Considering the results, the architecture reaches real time for HDTV 720p at 41 fps.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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