A full duplex implementation of Internet Protocol version 4 in an FPGA device

Abstract

This paper describes an implementation in hardware of Internet Protocol version 4. Routing and addressing features were integrated with Network Interfaces and synthesized to a Stratix II FPGA device. Our work showed two implementations of a full duplex Internet Protocol version 4. The first implementation consists in a Reference design and the second uses the same design but with more buffer space. We present the advantages and disadvantages of each implementation and also compare in terms of throughput, frame loss rate and power dissipation. The implementation with more buffer space presents a better performance in frame loss rate but it dissipates more power than the Reference design. Both implementations presented similar results for throughput tests.