Decimal division: Algorithms and FPGA implementations

Abstract

The work reported in this paper is devoted to the FPGA implementation of decimal dividers. Two types of dividers are described. The first one implements a decimal non-restoring like algorithm and uses ripple-carry operators. For medium size operators it gives a good compromise between cost and latency. The second one implements an SRT-like algorithm and uses carry-free operators. Their latencies are close to that of a binary radix-16 divider with the same range, implemented in the same FPGA.