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2012 24th International Symposium on Power Semiconductor Devices and ICs最新文献

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A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET 一个90至170V可扩展的P-LDMOS，附带高压PJFET
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229040
J. Ellis-Monaghan, Yun Shi, S. Sharma, N. Feilchenfeld, T. Letavic, R. Phelps, C. Hedges, D. Cook, J. Dunn
{"title":"A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET","authors":"J. Ellis-Monaghan, Yun Shi, S. Sharma, N. Feilchenfeld, T. Letavic, R. Phelps, C. Hedges, D. Cook, J. Dunn","doi":"10.1109/ISPSD.2012.6229040","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229040","url":null,"abstract":"A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121857332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Powwer supply on chip (integration of inductors and capacitors with active semiconductors) 片上电源(电感和电容与有源半导体的集成)
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229087
C. Mathuna, Ningning Wang, S. Kulkarni, Saibal Roy
{"title":"Powwer supply on chip (integration of inductors and capacitors with active semiconductors)","authors":"C. Mathuna, Ningning Wang, S. Kulkarni, Saibal Roy","doi":"10.1109/ISPSD.2012.6229087","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229087","url":null,"abstract":"The paper introduces the concept of power supply on chip (PwrSoC) which will enable the development of next generation, functionally integrated, power management platforms with applications in dc-dc conversion, gate drives, isolated power transmission and ultimately, high granularity, on-chip, power management for mixed-signal, SOC chips. PwrSoC will integrate power passives with the power management IC, in a 3D stacked or monolithic form factor, thereby delivering the performance of a high efficiency dc-dc converter within the footprint of a low efficiency linear regulator. A central element of the PwrSoC concept is the fabrication of power micro-magnetics on silicon to deliver micro-inductors and micro-transformers. The paper details the magnetics on silicon process which combines thin film magnetic core technology with electroplated copper conductors. Measured data for micro-inductors show inductance operation up to 20MHz, footprints down to 0.5mm2, efficiencies up to 93% and dc current carrying capability up to 600mA. Measurements on micro-transformers show voltage gain of approximately -1dB at between 10MHz and 30 MHz.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Planar dual gate oxide LDMOS structures in 180nm power management technology 180nm功率管理技术的平面双栅氧化LDMOS结构
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229107
S. Sharma, T. Letavic, Yun Shi, A. Loiseau, J. Monaghan, N. Feilchenfeld, R. Phelps, C. Lamothe, D. Cook, J. Dunn, G. Roerher, H. Nauschnig, R. Minixhofer
{"title":"Planar dual gate oxide LDMOS structures in 180nm power management technology","authors":"S. Sharma, T. Letavic, Yun Shi, A. Loiseau, J. Monaghan, N. Feilchenfeld, R. Phelps, C. Lamothe, D. Cook, J. Dunn, G. Roerher, H. Nauschnig, R. Minixhofer","doi":"10.1109/ISPSD.2012.6229107","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229107","url":null,"abstract":"This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BVds-Rsp, gm, HCI reliability, and forward safe operating area figures-of-merit. The planar dual gate structure exhibits BVds=32V/14 mΩ.mm2 specific on-resistance (and BVds=20V/7.5mΩ.mm2 for a drift length scaled version), hot carrier reliability in excess of 10 years analog lifetime in all bias regimes, and a linear forward IV characteristic. The planar dual gate architecture is scalable in rated voltage from 7V to 24V, and is an ideal component for the integration of USB switch, battery charging, backlighting, and PA envelope tracking mobile applications.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Study of electron and hole traps in freewheeling diodes for low loss and low reverse recovery surge voltage 用于低损耗和低反向恢复浪涌电压的自由旋转二极管电子和空穴阱的研究
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229098
Satoru Kameyama, Masafumi Hara, Tomohiro Kubo, F. Hirahara, Junpei Ebine, Koichi Murakami
{"title":"Study of electron and hole traps in freewheeling diodes for low loss and low reverse recovery surge voltage","authors":"Satoru Kameyama, Masafumi Hara, Tomohiro Kubo, F. Hirahara, Junpei Ebine, Koichi Murakami","doi":"10.1109/ISPSD.2012.6229098","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229098","url":null,"abstract":"The purpose of the research described in this paper is to achieve freewheeling diodes (FWDs) with low loss and low reverse recovery surge voltage (Vdsurge). This paper discusses the relationship between electron and hole traps and the electrical properties of FWDs. Samples with controlled conditions of electron and hole traps were fabricated by He irradiation and annealing. The trap conditions were evaluated by deep level transient spectroscopy (DLTS) and cathode luminescence (CL). The electrical properties of the samples were measured and simulated to analyze the samples. The analysis clarified that controlling trap conditions is essential when designing device DC and AC electrical properties as well as Vdsurge.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125860903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A driver IC for photovoltaic module-integrated DC/DC converters 一种用于光伏组件集成DC/DC变换器的驱动IC
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229022
T. Doorn, H. Bergveld, D. Buthker, C. Castello, A. de Jong, R. van Otten, K. de Waal, T. van Ansem, M. Dijkstra, I. Keekstra, J. Sneep
{"title":"A driver IC for photovoltaic module-integrated DC/DC converters","authors":"T. Doorn, H. Bergveld, D. Buthker, C. Castello, A. de Jong, R. van Otten, K. de Waal, T. van Ansem, M. Dijkstra, I. Keekstra, J. Sneep","doi":"10.1109/ISPSD.2012.6229022","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229022","url":null,"abstract":"Photovoltaic (PV) installations suffer from a disproportional decrease in output power in case irradiance differences are present in the system. The Delta converter improves the output power in such cases by routing current differences around the shaded substring or module. This paper presents a driver IC for the Delta converter that simultaneously reduces its cost and improves its reliability. The driver IC integrates the complete control loop, power supplies, protections and references. The driver IC demonstrated trouble-free operation for 3 months under real-life conditions in a PV installation with different shading patterns. Depending on the shading pattern the Delta converter energy gain was 8%-18%.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124073425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Linear drain current degradations of FG-pLEDMOS transistor under different AC stress conditions 不同交流应力条件下FG-pLEDMOS晶体管的线性漏极电流衰减
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229083
Qinsong Qian, Weifeng Sun, Siyang Liu, Longxing Shi, Wei Su, Zhengxin Xu, Shulang Ma
{"title":"Linear drain current degradations of FG-pLEDMOS transistor under different AC stress conditions","authors":"Qinsong Qian, Weifeng Sun, Siyang Liu, Longxing Shi, Wei Su, Zhengxin Xu, Shulang Ma","doi":"10.1109/ISPSD.2012.6229083","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229083","url":null,"abstract":"The linear drain current degradations of the Field Gate p-type Lateral Extended Drain MOS(FG-pLEDMOS)for different AC hot-carrier stress conditions have been experimentally investigated for the first time. It is noted that the hot-carrier degradation has closed relation with duty cycle and the degradation recovery phenomenon has been discovered in this novel device. The experimental results also show that the degradation strongly depends on the time of rising and falling edge of the gate signal pulse. The FG-pLEDMOS stressed at faster rising and falling edge will suffer from more serious hot-carrier degradation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Planar SONOS gate power MOSFET with an ultra-shallow body region 具有超浅体区的平面SONOS栅极功率MOSFET
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229031
Xianda Zhou, Hao Feng, J. Sin
{"title":"Planar SONOS gate power MOSFET with an ultra-shallow body region","authors":"Xianda Zhou, Hao Feng, J. Sin","doi":"10.1109/ISPSD.2012.6229031","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229031","url":null,"abstract":"In this paper, a planar silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) with a 0.3 μm ultra-shallow heavily doped p-body region is presented. The ultra-shallow body provides a much reduced parasitic JFET resistance, resulting in a low specific on-resistance of 18 mΩ·mm2 for a planar device. At the same time, no punch-through problem is caused by the ultra-shallow body, and the avalanche breakdown voltage of the device is 29.5 V. The product of the on-resistance and gate charge of the ultra-shallow body SG-MOSFET is 43 mΩ·nC at VGS = 4.5 V. The non-optimized performance obtained for this structure is comparable to that of trench power MOSFETs fabricated using more advanced technologies.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accurate spice modeling of 80V power LDMOS with interdigitated source structure 具有交叉源结构的80V功率LDMOS的精确spice建模
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229033
Yukio Tamegaya, Risho Koh, Yukichi Hatanaka, Takahiro Iizuka
{"title":"Accurate spice modeling of 80V power LDMOS with interdigitated source structure","authors":"Yukio Tamegaya, Risho Koh, Yukichi Hatanaka, Takahiro Iizuka","doi":"10.1109/ISPSD.2012.6229033","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229033","url":null,"abstract":"This paper discusses a circuit simulation model for interdigitated source LDMOS. As p+ well contacts are inserted to the source regions, the device achieves high breakdown immunity without using high voltage p+ implantation under the source. However, since the parasitic resistance near the source p+ region is not formulated in the conventional compact model, the accuracy of the model is an issue. To solve this problem, this paper proposes a macro model, in which parasitic resistance near the p+ region is represented by an effective resistance (Rs). The formulation of Rs is discussed and the feasibility of the model is demonstrated.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124521652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel lateral 700V DMOS for integration: Ultra-low 85 mΩ ·cm2 on-resistance, 750V LFCC 新型横向700V DMOS集成:超低85 mΩ·cm2导通电阻，750V LFCC
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229054
Sunglyong Kim, Jongjib Kim, H. Prosack
{"title":"Novel lateral 700V DMOS for integration: Ultra-low 85 mΩ ·cm2 on-resistance, 750V LFCC","authors":"Sunglyong Kim, Jongjib Kim, H. Prosack","doi":"10.1109/ISPSD.2012.6229054","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229054","url":null,"abstract":"A new device concept which is able to break through the silicon limit has been introduced. LFCC (Lateral Floating-Capacitor-Coupled) structure with lateral trench array along drift layer makes drift dose higher than normal RESURF structure with high breakdown voltage. Three dimensional capacitive coupling helps electric field over drift region obtain trapezoidal shape which results in high breakdown voltage with relatively short drift length. Experimental results showed 85 mΩ·cm2 of specific Ron with 750V of breakdown voltage.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"23 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124555236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Reliability study of ONO gate film in high speed PTOx-TMOS based on electrical characteristics under high electric field 基于电场特性的高速pxo - tmos ONO栅膜可靠性研究
2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI: 10.1109/ISPSD.2012.6229035
E. Taktani, T. Arakawa, T. Aoki, M. Ogino
{"title":"Reliability study of ONO gate film in high speed PTOx-TMOS based on electrical characteristics under high electric field","authors":"E. Taktani, T. Arakawa, T. Aoki, M. Ogino","doi":"10.1109/ISPSD.2012.6229035","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229035","url":null,"abstract":"The purpose of this study is to clarify the more reliable design for ONO Gate insulator film for Trench Gate MOSFET. Partially Thick Oxide Trench Gate MOSFET (PTOx-TMOS) with ONO Gate film can reduce the Ron*Qgd Figure of Merit on easy process and simple structure. However this structure is required the appropriate design to prevent threshold voltage shift originated in charge storage effect. In this study, charge storage mechanism is analyzed experimentally and theoretically with the Fowler-Nordheim and Direct-Tunneling electric conduction behavior in high electric field.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"33 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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