A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET

2012 24th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2012-06-03 DOI:10.1109/ISPSD.2012.6229040

J. Ellis-Monaghan, Yun Shi, S. Sharma, N. Feilchenfeld, T. Letavic, R. Phelps, C. Hedges, D. Cook, J. Dunn

引用次数: 1

Abstract

A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.

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一个90至170V可扩展的P-LDMOS，附带高压PJFET

提出了一种新的横向缩放P-LDMOS器件的JFET设计。P-LDMOS器件具有优异的Rsp，因为它可以从90V缩放到170V工作。该P-LDMOS设计经过改进，可产生100V的PJFET，具有良好的关断特性和相对较低的3-7V电压。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 24th International Symposium on Power Semiconductor Devices and ICs

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