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2011 IEEE Workshop on Signal Processing Systems (SiPS)最新文献

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Stochastic modeling for floating-point to fixed-point conversion 浮点到定点转换的随机建模
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088971
A. Banciu, E. Casseau, D. Ménard, Thierry Michel
{"title":"Stochastic modeling for floating-point to fixed-point conversion","authors":"A. Banciu, E. Casseau, D. Ménard, Thierry Michel","doi":"10.1109/SiPS.2011.6088971","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088971","url":null,"abstract":"The floating-point to fixed-point transformation process is error prone and time consuming as the distortion introduced by the limited data size is difficult to evaluate. In this paper a method to estimate the range of variables in LTI systems with respect to the corresponding overflow probability is presented. Furthermore, we will show that the quantization noise evaluation can be realized using the same approach. The variance and the probability density function of the error are computed. The results obtained for several typical applications are presented.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121060212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Highly scalable implementation of a robust MMSE channel estimator for OFDM multi-standard environment 一种用于OFDM多标准环境的鲁棒MMSE信道估计器的高可扩展性实现
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088995
I. Diaz, B. Sathyanarayanan, A. Malek, F. Foroughi, J. Rodrigues
{"title":"Highly scalable implementation of a robust MMSE channel estimator for OFDM multi-standard environment","authors":"I. Diaz, B. Sathyanarayanan, A. Malek, F. Foroughi, J. Rodrigues","doi":"10.1109/SiPS.2011.6088995","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088995","url":null,"abstract":"In this paper a VLSI implementation of a highly scalable MMSE (Minimum Mean Square Estimator) is presented with the ultimate goal of demonstrating the potential of MMSE as enabler for multi-standard channel estimation. By selecting an appropriate implementation, a complexity reduction of 98% is achieved when compared to Time-Domain Maximum Likelihood Estimation (TDMLE), whereas low power consumption is accomplished by implementing a low-power-mode. The architecture is capable of performing Least Square (LS) estimation and MMSE compliant with 3GPP LTE (Long Term Evolution), IEEE 802.11n (WLAN), and DVB-H (Digital Video Broadcast for Handheld Devices), The estimator is synthesized using a 65nm low-leakage high-threshold standard-cell CMOS library. The design occupies an area of 0.169 mm2, is capable of running upto 250 MHz, providing a throughput of 78M estimates/second. Simulations under a typical LTE reception show that the implementation dissipates 4.9μW per sample.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128452202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improved crosstalk avoidance codes based on a novel pattern classification 基于新型模式分类的改进串扰避免码
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088982
Feng Shi, Xuebin Wu, Zhiyuan Yan
{"title":"Improved crosstalk avoidance codes based on a novel pattern classification","authors":"Feng Shi, Xuebin Wu, Zhiyuan Yan","doi":"10.1109/SiPS.2011.6088982","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088982","url":null,"abstract":"The crosstalk delay associated with global on-chip interconnects becomes more serious in deep submicrometer technology, and hence can greatly affect the overall system performance. Based on a delay model proposed by Sotiriadis et al., crosstalk avoidance codes (CACs) have been proposed to alleviate the crosstalk delays by restricting the patterns transmitted on the interconnects. Unfortunately, the effectiveness of these CACs is limited by some drawbacks of the model by Sotiriadis et al. In this paper, we first propose a new classification of transition patterns based on a 5-bit bus, and then provide a method to design CACs with our classification. To illustrate our method, we present a crosstalk avoidance code which achieves a smaller worst-case delay than existing CACs.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Methodology for the hardware/software co-design of dataflow programs 数据流程序的硬件/软件协同设计方法
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088970
Ghislain Roquier, Richard Thavot, M. Mattavelli
{"title":"Methodology for the hardware/software co-design of dataflow programs","authors":"Ghislain Roquier, Richard Thavot, M. Mattavelli","doi":"10.1109/SiPS.2011.6088970","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088970","url":null,"abstract":"New generations of multi-core processors and reconfigurable hardware platforms are expected to provide a dramatic increase of processing capabilities. However, one obstacle for exploiting all the promises of such new platforms is the legacy of current applications and the development methodologies used, which is deeply rooted in a sequential way of thinking. A paradigm shift is necessary at all levels of application development to yield portable and efficient implementations, capable of exploiting the full potential of such platforms. Dataflow programming is an alternative approach that address the problem of providing portable and scalable parallel applications. Dataflow programming is able to explicitly expose the intrinsic parallelism of applications. This paper presents a hardware/software co-design methodology that starting from a unique dataflow program enables, by the direct synthesis of both hardware (HDL) and software components (C/C++), to map a signal processing application onto heterogeneous systems architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of the MPEG-4 Simple Profile decoder onto an heterogeneous platform are also provided to show the capabilities and flexibility of the approach.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Beamforming for interference mitigation and its implementation on an SDR baseband processor 干扰抑制的波束形成及其在SDR基带处理器上的实现
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088973
Adrian Krdu, Y. Lebrun, U. Ahmad, S. Pollin, Prashant Agrawal, Min Li
{"title":"Beamforming for interference mitigation and its implementation on an SDR baseband processor","authors":"Adrian Krdu, Y. Lebrun, U. Ahmad, S. Pollin, Prashant Agrawal, Min Li","doi":"10.1109/SiPS.2011.6088973","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088973","url":null,"abstract":"We present the first implementation of a distributed beam-forming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to implement in practical scenarios due to their complexity and synchronization requirements. In this paper, we report on implementation of a suboptimal, yet efficient, beamforming scheme for CCI mitigation and present the complexity modeling and algorithm transformations for achieving numerically stability. We also present the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). We optimize this algorithm for a coarse grained reconfigurable array (CGRA) processor and evaluate it in the context of the LTE standard.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133284120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A hardware architecture for accelerating neuromorphic vision algorithms 一种加速神经形态视觉算法的硬件架构
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6089002
Ahmed Al-Maashri, M. DeBole, Chi-Li Yu, N. Vijaykrishnan, C. Chakrabarti
{"title":"A hardware architecture for accelerating neuromorphic vision algorithms","authors":"Ahmed Al-Maashri, M. DeBole, Chi-Li Yu, N. Vijaykrishnan, C. Chakrabarti","doi":"10.1109/SiPS.2011.6089002","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6089002","url":null,"abstract":"Neuromorphic vision algorithms are biologically inspired algorithms that follow the processing that takes place in the visual cortex. These algorithms have proved to match classical computer vision algorithms in classification performance and even outperformed them in some instances. However, neuromorphic algorithms suffer from high complexity leading to poor execution times when running on general purpose processors, making them less attractive for real-time applications. FPGAs, on the other hand, have become true signal processing platforms due to their lightweight, low power consumption and massive parallel computational resources. This paper describes an FPGA-based hardware architecture that accelerates an object classification cortical model, HMAX. Compared to a CPU implementation, this hardware accelerator offers 23X (89X) speedup when mapped to a single-FPGA (multi-FPGA) platform, while maintaining a classification accuracy of 92.5%.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"59 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124317338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Energy-efficient XOR gate with embedded level conversion for serial-link encoding 具有嵌入式电平转换串行链路编码的节能异或门
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088964
J. Tessier, Randa Ayoubi, M. Bayoumi
{"title":"Energy-efficient XOR gate with embedded level conversion for serial-link encoding","authors":"J. Tessier, Randa Ayoubi, M. Bayoumi","doi":"10.1109/SiPS.2011.6088964","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088964","url":null,"abstract":"The insatiable demand for increased energy-efficient communication bandwidth has led to the widespread adoption of serial-links. Serializer/Deserializer (SerDes) architectures have seen considerable use in both inter — and intra-chip communication of high-performance computing platforms and embedded systems. Serializers translate m-bit parallel data into a serial stream of increased data rate. Bus encoding can lower the activity factor of the link to mitigate energy consumption. Additional savings can be gained by partitioning the supply voltage at the serializer boundary to capitalize on the difference in parallelism. However, the required voltage level conversion increases complexity and delay. In this work, a new method of gate-embedded level conversion is demonstrated within a XOR gate for the purpose of constructing a serializer-encoder. We explore existing level converters, as well as, the ramifications of level conversion before and after serial bus encoding. Results show the complementary pass-transistor logic (CPL)-based level converters have the best energy delay product (EDP) of those compared yielding 0.8fJ/bit at 4Gb/s.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digit recognition with confidence 自信的数字识别
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088993
G. Sakr, I. Elhajj
{"title":"Digit recognition with confidence","authors":"G. Sakr, I. Elhajj","doi":"10.1109/SiPS.2011.6088993","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088993","url":null,"abstract":"Assigning a confidence measure is a challenging stochastic inference problem. Some algorithms only yield the predicted value without evaluating the measure of confidence over the decision. Support vector machines is one algorithm that showed state of the art decision accuracy but lacks a measure of confidence over the decisions. In this paper we propose a confidence measure based on the VC (Vapnik and Chervonenkis) dimension of a learning algorithm. The resulting confidence measure is then tested on the well known US postal handwritten digit recognition. The results show high and improved correlation between the decision and the confidence measure.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130556889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Embedded transition inversion coding for low power serial link 嵌入式低功耗串行链路转换反转编码
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088957
Wen-Chih Huang, Chih-Hsing Lin, C. Chiu
{"title":"Embedded transition inversion coding for low power serial link","authors":"Wen-Chih Huang, Chih-Hsing Lin, C. Chiu","doi":"10.1109/SiPS.2011.6088957","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088957","url":null,"abstract":"Serial link interconnection has generated a lot of attention in on-chip bus design due to its advantages over multibit parallel interconnection in terms of crosstalk, skew, and area cost. However, serializing a multi-bit parallel bus tends to increase the bit transition and power dissipation. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to address the problem of the extra indication bit. This ETI coding scheme reduces the transition by up to 31% compared with the encoding followed by serial (ES) scheme. The analysis and simulation results, in this study indicate that the proposed coding scheme produces a low bit transition for different kinds of data pattern.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116838986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An area-efficient symbol deinterleaver architecture for DVB-T 一种适用于DVB-T的面积高效符号去交织器结构
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088965
Hamid Reza Tanhaei, M. Rezaee
{"title":"An area-efficient symbol deinterleaver architecture for DVB-T","authors":"Hamid Reza Tanhaei, M. Rezaee","doi":"10.1109/SiPS.2011.6088965","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088965","url":null,"abstract":"A new architecture has been proposed for the symbol deinterleaver used in DVB-T channel decoder. In conventional architecture of the symbol deinterleaver two separate single-port RAMs have been used for buffering odd and even OFDM symbols. In this paper we show that these two RAMs can be merged so that only one single-port RAM for buffering of both odd and even symbols would be used and hence the required memory space will be reduced by half. Also, an architecture for address generator has been designed for generating consecutive valid addresses. Due to the simplicity of the proposed architecture, it can be easily implemented; however, the operation clock-frequency doubled with respect to the conventional two-RAM architecture.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127140297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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