Energy-efficient XOR gate with embedded level conversion for serial-link encoding

Abstract

The insatiable demand for increased energy-efficient communication bandwidth has led to the widespread adoption of serial-links. Serializer/Deserializer (SerDes) architectures have seen considerable use in both inter — and intra-chip communication of high-performance computing platforms and embedded systems. Serializers translate m-bit parallel data into a serial stream of increased data rate. Bus encoding can lower the activity factor of the link to mitigate energy consumption. Additional savings can be gained by partitioning the supply voltage at the serializer boundary to capitalize on the difference in parallelism. However, the required voltage level conversion increases complexity and delay. In this work, a new method of gate-embedded level conversion is demonstrated within a XOR gate for the purpose of constructing a serializer-encoder. We explore existing level converters, as well as, the ramifications of level conversion before and after serial bus encoding. Results show the complementary pass-transistor logic (CPL)-based level converters have the best energy delay product (EDP) of those compared yielding 0.8fJ/bit at 4Gb/s.