2011 IEEE Workshop on Signal Processing Systems (SiPS)最新文献

A neural networks approach to interval-valued data clustering. Applicationto Lebanese meteorological stations data 区间值数据聚类的神经网络方法。黎巴嫩气象站资料的应用

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6089005

H. Hamdan, Chantal Hajjar

引用次数: 8

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering 一种基于专用矩阵重排序的高并行宏块级分层LDPC解码结构

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088961

Q. Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, S. Goto

引用次数: 6

Fast computation of Gaussian likelihoods using low-rank matrix approximations 使用低秩矩阵近似快速计算高斯似然

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088983

Mrugesh R. Gajjar, T. Sreenivas, R. Govindarajan

{"title":"Fast computation of Gaussian likelihoods using low-rank matrix approximations","authors":"Mrugesh R. Gajjar, T. Sreenivas, R. Govindarajan","doi":"10.1109/SiPS.2011.6088983","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088983","url":null,"abstract":"Acoustic modeling using mixtures of multivariate Gaussians is the prevalent approach for many speech processing problems. Computing likelihoods against a large set of Gaussians is required as a part of many speech processing systems and it is the computationally dominant phase for LVCSR systems. We express the likelihood computation as a multiplication of matrices representing augmented feature vectors and Gaussian parameters. The computational gain of this approach over traditional methods is by exploiting the structure of these matrices and efficient implementation of their multiplication. In particular, we explore direct low-rank approximation of the Gaussian parameter matrix and indirect derivation of low-rank factors of the Gaussian parameter matrix by optimum approximation of the likelihood matrix. We show that both the methods lead to similar speedups but the latter leads to far lesser impact on the recognition accuracy. Experiments on a 1138 word vocabulary RM1 task using Sphinx 3.7 system show that, for a typical case the matrix multiplication approach leads to overall speedup of 46%. Both the low-rank approximation methods increase the speedup to around 60%, with the former method increasing the word error rate (WER) from 3.2% to 6.6%, while the latter increases the WER from 3.2% to 3.5%.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Scheduling of dynamic dataflow programs with model checking 具有模型检查的动态数据流程序调度

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088946

Johan Ersfolk, Ghislain Roquier, F. Jokhio, J. Lilius, M. Mattavelli

引用次数: 19

An information-theoretic framework for joint architectural and circuit level optimization for olfactory recognition processing 嗅觉识别处理联合架构和电路级优化的信息理论框架

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088943

Ping-Chen Huang, D. Macii, J. Rabaey

引用次数: 0

Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation 基于全局运动估计和补偿的高清视频帧率上转换硬件架构设计

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088955

Kung-Yen Hsu, Shao-Yi Chien

{"title":"Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation","authors":"Kung-Yen Hsu, Shao-Yi Chien","doi":"10.1109/SiPS.2011.6088955","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088955","url":null,"abstract":"Frame rate up-conversion (FRUC) with motion compensated interpolation (MCI) is a key operation for motion blur reduction on liquid crystal displays, and dedicated hardware engine design is necessary. In this paper, a hardware architecture for real-time FRUC applications is designed with global motion estimation and compensation. With the concept of motion estimation in low resolution and motion compensation in high resolution, and redesigning several memory bandwidth-hungry modules, a previous work, global-to-local iterative MCI, is modified for hardware design with similar subjective performance. Next, a high-throughput global motion estimation (GME) engine is designed with subsampling technique and parallel hardware architecture, and global motion compensated interpolation and moving block classifier are both designed by sharing the hardware with GME. Moreover, a motion estimation engine is also designed to support various local motion estimation algorithms in different stages. Implementation results show that the proposed GME engine can achieve much higher specifications with limited hardware cost increase. Furthermore, the proposed FRUC design can generate 60 1920 × 1080 interpolated frames per second with the gate count of 1.3M and on-chip memory size of 99kb.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Methodology and technique to improve throughput of FPGA-based Cal dataflow programs: Case study of the RVC MPEG-4 SP Intra decoder 提高基于fpga的Cal数据流程序吞吐量的方法和技术:RVC MPEG-4 SP内部解码器的案例研究

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088972

Hossam Amer, A. Rahman, I. Amer, Christophe Lucarz, M. Mattavelli

引用次数: 10

New hardware Cryptosystem based chaos for the secure real-time of embedded applications 基于混沌的新型硬件密码系统，实现嵌入式应用的安全实时性

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088984

M. S. Azzaz, C. Tanougast, S. Sadoudi, A. Dandache

引用次数: 9

Vectorization and mapping of software defined radio applications on heterogeneous multi-processor platforms 异构多处理器平台上软件无线电应用的矢量化和映射

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088945

G. Zaki, W. Plishker, S. Bhattacharyya, T. Clancy, J. Kuykendall

引用次数: 9

VLSI architecture for soft-output tuple search sphere decoding 软输出元组搜索球解码的VLSI架构

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088978

Esther P. Adeva, M. A. Shah, B. Mennenga, G. Fettweis

{"title":"VLSI architecture for soft-output tuple search sphere decoding","authors":"Esther P. Adeva, M. A. Shah, B. Mennenga, G. Fettweis","doi":"10.1109/SiPS.2011.6088978","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088978","url":null,"abstract":"High detection complexity is known to be one of the major challenges in MIMO communications based on spatial multiplexing. Tuple Search Detector (TSD) was recently introduced, significantly reducing detection complexity in comparison to conventional algorithms while achieving close to full max-log-APP BER performance. Irregular control flow and sequential nature of depth-first-based detectors frustrate efficient application of parallelization techniques, typically leading to inefficient realizations. This work presents a novel TSD implementation, based on a scalable and parallelizable pipelined ASIP architecture. The proposed VLSI design is implemented for 4×4 MIMO transmission using 64-QAM constellation on 65-nm CMOS technology. In low SNR scenarios, proposed detector achieves 403.6 Mbps throughput at 454 MHz clock frequency. TSD can be moreover adjusted according to transmission conditions, reaching >1 Gbps. A silicon area of 0.14 mm2 (98.9 kGEs) is occupied by the TSD core, reporting low power dissipation (57.94 mW) under typical case operating conditions. Proposed detector implementation achieves close to full max-log-APP BER performance and high detection throughput with reasonable hardware complexity, by far outperforming state-of-the-art realizations.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132827635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9