2011 IEEE Workshop on Signal Processing Systems (SiPS)最新文献_第4页

EVA-MAC: An event-based adaptive medium access control for wireless sensor networks EVA-MAC:一种基于事件的无线传感器网络自适应介质访问控制

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088950

Z. Merhi, M. Elgamel, M. Bayoumi

引用次数: 0

High level analysis of trade-offs across different partitioning schemes for wireless applications 对无线应用程序的不同分区方案进行高级分析

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088967

Prashant Agrawal, Robert Fasthuber, P. Raghavan, T. Aa, U. Ahmad, L. Perre, F. Catthoor

引用次数: 1

A comparative study of pre-image techniques: The kernel autoregressive case 预图像技术的比较研究:核自回归情况

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6089006

Maya Kallas, P. Honeine, C. Francis, H. Amoud

{"title":"A comparative study of pre-image techniques: The kernel autoregressive case","authors":"Maya Kallas, P. Honeine, C. Francis, H. Amoud","doi":"10.1109/SiPS.2011.6089006","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6089006","url":null,"abstract":"The autoregressive (AR) model is one of the most used techniques for time series analysis, applied to study stationary as well as non-stationary processes. However, being a linear technique, it is not adapted for nonlinear systems. Recently, we introduced the kernel AR model, a straightforward extension of the AR model to the nonlinear case. It is based on the concept of kernel machines, where data are nonlinearly mapped from the input space to a feature space. The AR model can thus be applied on the mapped data. Nevertheless, in order to predict future samples, one needs to go back to the input space, by solving the pre-image problem. The prediction performance highly depends on the considered pre-image technique. In this paper, a comparative study of several state-of-the-art pre-image techniques is conducted for the kernel AR model, investigating the prediction error with the optimal model parameters, as well as the computational complexity. The conformal map approach presents results as good as the well known fixed-point iterative method, with less computational time. This is shown on unidimensional and multidimensional chaotic time series.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121863257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Reconfigurable cache memory architecture for integral image and integral histogram applications 用于积分图像和积分直方图应用的可重构缓存存储器架构

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088966

Po-Hao Hsu, Shao-Yi Chien

{"title":"Reconfigurable cache memory architecture for integral image and integral histogram applications","authors":"Po-Hao Hsu, Shao-Yi Chien","doi":"10.1109/SiPS.2011.6088966","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088966","url":null,"abstract":"Cache memory can reduce the memory latency between processor and off-chip DRAM, and it usually occupies a large area of the whole system. However, for accessing integral images and integral integral histograms, which are famous for getting an arbitrary-sized block summation and histogram in a constant speed and widely implemented in many applications, the read and write mechanisms of cache are not suitable for such algorithms with stream processing characteristic. In this paper, a reconfigurable cache memory architecture is proposed with two modes: normal cache mode and Row-Based Stream Processing (RBSP) mode, which is a specific memory architecture for data accessing of integral images and integral histograms. Moreover, the data reuse scheme between different filter sizes and different rows are taken into consideration to further reduce the data access to the off-chip DRAM. In addition, a method called Memory Dividing Technique (MDT) is also proposed to further reduce the word-length. SURF algorithm and center-surround histogram salience map are implemented to verify the proposed design. The experimental results show that the proposed architecture can save 89.15% and 68.12% memory read cycle count for these two applications compared to the traditional fully-associative cache in the same memory size.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117160896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Optimization of portable parallel signal processing applications by design space exploration of dataflow programs 通过数据流程序的设计空间探索优化便携式并行信号处理应用

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088947

Christophe Lucarz, M. Mattavelli, J. Janneck

引用次数: 6

Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems 利用数据的算术表示特性，减少无线OFDM系统FFT电路的面积和功耗

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088941

A. Brokalakis, Vassilis Paliouras

引用次数: 4

Compressed sensing based MR image reconstruction from multiple partial K-space scans 基于压缩感知的多局部k空间磁共振图像重建

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088999

A. Majumdar, R. Ward

引用次数: 3

Saliency prediction using scene motion for JND based video compression 基于场景运动的JND视频压缩显著性预测

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088952

R. Wang, C. Chiu

引用次数: 2

Hardware efficiency versus error probability in unreliable computation 不可靠计算中的硬件效率与错误概率

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088969

Yangyang Tang, E. Boutillon, C. Jégo, M. Jézéquel

引用次数: 5

Combining LDPC, turbo and Viterbi decoders: Benefits and costs 结合LDPC，涡轮和维特比解码器:效益和成本

2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088977

S. Kunze, E. Matús, G. Fettweis, T. Kobori

引用次数: 7