发布求助
文献互助 智能选刊 最新文献

2011 IEEE Workshop on Signal Processing Systems (SiPS)最新文献

筛选
英文 中文
Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems 结合时空信息和特征杂波滤波的自适应阈值法用于超声系统的彩色多普勒处理
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6089003
Cheng-Zhou Zhan, Zih-Ling Liu, A. Wu
{"title":"Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems","authors":"Cheng-Zhou Zhan, Zih-Ling Liu, A. Wu","doi":"10.1109/SiPS.2011.6089003","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6089003","url":null,"abstract":"Color Doppler imaging is mainly used to observe the blood flow in the region of interest. The desired blood signal will be greatly affected by the clutter noises, and conventional linear clutter filter may not eliminate clutter noises effectively without the assistance of the thresholding mechanism. In this work, we proposed an adaptive thresholding mechanism with probability-based clutter power ratio (PCPR) incorporating temporal and spatial information based on the maximum-likelihood (ML) and maximum a posteriori (MAP) criteria. The proposed mechanism can verify the blood and tissue regions more accurately and eliminate all the undesired clutter noises in the verified tissue regions. The proposed mechanism has 5-10 dB better performance than the referenced algorithms due to its nonlinear property.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113996069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping 用于DVB-T2标准的打乱迭代位交错编码调制接收机:设计、实现和FPGA原型设计
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088949
Meng Li, C. A. Nour, C. Jégo, Jianxiao Yang, C. Douillard
{"title":"A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping","authors":"Meng Li, C. A. Nour, C. Jégo, Jianxiao Yang, C. Douillard","doi":"10.1109/SiPS.2011.6088949","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088949","url":null,"abstract":"Rotated QAM constellations improve Bit-Interleaved Coded Modulation (BICM) performance over fading channels. Indeed, an increased diversity is obtained by coupling a constellation rotation with interleaving between the real and imaginary components of transmitted symbols either in time or frequency domain. Iterative processing at the receiver side can provide additional improvement in performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. Scheduling an efficient message passing algorithm with low latency between the demapper and the LDPC decoder represents the main contribution. The design and the FPGA prototyping of the resultant shuffled iterative BICM receiver are then described. Architecture complexity and measured performance validate the potential of iterative receiver as a practical and competitive solution for the DVB-T2 standard.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"97 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134477834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low-power adder design techniques for noise-tolerant applications 用于耐噪应用的低功耗加法器设计技术
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088960
Ihab Nahlus, Lama Shaer, A. Chehab, A. Kayssi, Mohammad M. Mansour
{"title":"Low-power adder design techniques for noise-tolerant applications","authors":"Ihab Nahlus, Lama Shaer, A. Chehab, A. Kayssi, Mohammad M. Mansour","doi":"10.1109/SiPS.2011.6088960","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088960","url":null,"abstract":"In the nanometer era, there is a critical need for low power design. In this paper we employ voltage scaling in a new sophisticated manner to reduce the power consumption of a particular circuit targeted for noise-tolerant applications. We show that we can save up to 40 times in power consumption in the case of applications that can tolerate long delays. On the other hand, we investigate how far we can reduce the power consumption of a circuit without affecting its speed of operation. Our results show 58% and 168% reduction in the power consumption when using multi supply voltages, with the drawback of having some errors in the major reduction technique (168%) which could be suitable for applications that can tolerate some loss of accuracy such as the case in stochastic processing. For such applications, we also show that we can even go further into power savings by eliminating altogether the least significant part of our circuit and hence accepting errors for an additional savings of 41% over the savings in the previous methods.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116457004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PCA and KPCA of ECG signals with binary SVM classification 基于二值支持向量机分类的心电信号主成分分析和主成分分析
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6089000
Lara Kanaan, D. Merheb, Maya Kallas, C. Francis, H. Amoud, P. Honeine
{"title":"PCA and KPCA of ECG signals with binary SVM classification","authors":"Lara Kanaan, D. Merheb, Maya Kallas, C. Francis, H. Amoud, P. Honeine","doi":"10.1109/SiPS.2011.6089000","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6089000","url":null,"abstract":"Cardiac problems are the main reason of people's death nowadays. However, one way that light save the life is the analysis of the an electrocardiograph. This analysis consist in the diagnosis of the arrhythmia when it presents. In this paper, we propose to combine the Support Vector Machines used in classification on one hand, with the Principal Component Analysis used in order to reduce the size of the data by choosing some axes that capture the most variance between data and on the other hand, with the kernel principal component analysis where a mapping to a high dimensional space is needed to capture the most relevant axes but for nonlinear separable data. The efficiency of the proposed SVM classification is illustrated on real electrocardiogram dataset taken from MIT-BIH Arrhythmia Database.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122745847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Reduced complexity Chase-Pyndiah decoding algorithm for turbo product codes turbo积码的降低复杂度Chase-Pyndiah译码算法
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088976
Junhee Cho, Wonyong Sung
{"title":"Reduced complexity Chase-Pyndiah decoding algorithm for turbo product codes","authors":"Junhee Cho, Wonyong Sung","doi":"10.1109/SiPS.2011.6088976","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088976","url":null,"abstract":"Turbo product codes (TPC) are very suitable for applications requiring a large code length, a high code-rate, and good error performance. In the Chase decoding algorithm, normally a few least reliable positions are selected and the test sequences are generated from these positions. This paper proposes two methods to lower the complexity of the Chase-Pyndiah decoding algorithm. The first scheme reduces the number of least reliable positions by excluding those having relatively low error probabilities. The other one minimizes computations on unnecessary positions in an algebraic decoder. With these methods, we can significantly reduce the number of test sequences and lower the number of utilized positions for constructing an extended candidate codeword set. We show the simulation results with a squared (64, 57, 4) extended Hamming code-based TPC.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127800231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Flexible product code-based ECC schemes for MLC NAND Flash memories MLC NAND闪存灵活的基于产品代码的ECC方案
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088985
Chengen Yang, Yunus Emre, C. Chakrabarti, T. Mudge
{"title":"Flexible product code-based ECC schemes for MLC NAND Flash memories","authors":"Chengen Yang, Yunus Emre, C. Chakrabarti, T. Mudge","doi":"10.1109/SiPS.2011.6088985","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088985","url":null,"abstract":"Error control coding (ECC) is essential for correcting soft errors in Flash memories. In such memories, as the number of erase/program cycles increases over time, the number of errors increases. In this paper we propose a flexible product code based ECC scheme that can support ECC of higher strength when needed. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns. When higher ECC is needed, the Hamming code along columns is replaced by two shorter Hamming codes. For instance, when the raw bit error rate increases from 2.2∗10−3 to 4.0∗10−3, the proposed ECC scheme migrates from RS(127, 121) along rows and Hamming(72,64) along columns to RS(127, 121) along rows and two Hamming(39, 32) along columns to achieve the same BER of 10−6. While the resulting implementation has 12% higher decoding latency, it increases the lifetime of the device significantly.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129207024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Frequency domain: Efficient and high speed technology for video transmission 频域:高效、高速的视频传输技术
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088989
Y. Ismail, S. El-Etriby, M. Bayoumi
{"title":"Frequency domain: Efficient and high speed technology for video transmission","authors":"Y. Ismail, S. El-Etriby, M. Bayoumi","doi":"10.1109/SiPS.2011.6088989","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088989","url":null,"abstract":"Motion Estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Using DCT along with Adaptive Padding (AP) in frequency domain are the recently evolved Frequency Domain ME (FDME) techniques that efficiently reduce the ME computational complexity. There are two main problems of using such conventional AP in the frequency domain. Firstly, the adaptive thresholds need to be estimated in the pixel (IDCT) domain which increases complexity. Secondly, the mismatched transformed search area is formed from different successive transformed blocks, which would lead to an inaccurate ME if the search area is not manipulated. In this paper, an efficient low complexity algorithm and high speed architecture are proposed to implement an adaptive Manipulation Unit (MU). The MU, the main module of the FDME system, adaptively decides the padding size and forges a matched transformed search area from the successive transformed blocks. Additionally, the proposed utilized adaptive thresholds are efficiently estimated in the Frequency Domain (FD). The MU architecture is presented with two different design implementations trading off the VLSI design parameters.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127024336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient multicore scheduling of dataflow process networks 数据流处理网络的高效多核调度
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088974
H. Yviquel, E. Casseau, M. Wipliez, M. Raulet
{"title":"Efficient multicore scheduling of dataflow process networks","authors":"H. Yviquel, E. Casseau, M. Wipliez, M. Raulet","doi":"10.1109/SiPS.2011.6088974","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088974","url":null,"abstract":"Although multi-core processors are now available everywhere, few applications are able to truly exploit their multiprocessing capabilities. Dataflow programming attempts to solve this problem by expressing explicit parallelism within an application. In this paper, we describe two scheduling strategies for executing a dataflow program on a single-core processor. We also describe an extension of these strategies on multi-core architectures using distributed schedulers and lock-free communications. We show the efficiency of these scheduling strategies on MPEG-4 Simple Profile and MPEG-4 Advanced Video Coding decoders.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127344967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Robustness and expression independence in 3D face recognition 三维人脸识别中的鲁棒性和表情独立性
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088991
S. Miao, H. Krim
{"title":"Robustness and expression independence in 3D face recognition","authors":"S. Miao, H. Krim","doi":"10.1109/SiPS.2011.6088991","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088991","url":null,"abstract":"We describe a robust method for 3D face recognition under variance of facial expressions. The method utilizes the identical areas on two facial images as the measurement of distance. To segment the identical area, partial shape matching is performed using closest point registration and level set method. The segmentation problem is formalized into an Eikonal equation, which can be efficiently solved by fast marching method. The presented 3D face recognition method shows a very promising recognition rate.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121976471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fast modified Horn & Schunck method for the estimation of optical flow fields 快速修正的Horn & Schunck光流场估计方法
2011 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2011-12-01 DOI: 10.1109/SiPS.2011.6088990
Z. Baarir, F. Charif
{"title":"Fast modified Horn & Schunck method for the estimation of optical flow fields","authors":"Z. Baarir, F. Charif","doi":"10.1109/SiPS.2011.6088990","DOIUrl":"https://doi.org/10.1109/SiPS.2011.6088990","url":null,"abstract":"This paper presents a fast, accurate and reliable modified Horn & Schunck approach for robust boundary preserving estimation of optical flow where only 30 iterations are used. The proposed method is derived from the benchmark algorithm of Horn & Schunck and Simoncelli's matched-pair 5 tap filters, such that it produces robust, fast and exact detection of motion boundaries and it is very simple to implement. Experimental results using synthetic and real optical flows are presented to demonstrate the effectiveness of our method in comparison to selected methods.","PeriodicalId":368538,"journal":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书