2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献_第3页

The path to global connectivity — Wireless communication enters the next generation 全球连接之路——无线通信进入下一代

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226040

J. Hausner

引用次数: 0

Automated, inter-macro channel space adjustment and optimization for faster design closure 自动，宏间通道空间调整和优化，更快的设计关闭

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226010

Praveen Kumar, Alexander Fell, Sachin Mathur

{"title":"Automated, inter-macro channel space adjustment and optimization for faster design closure","authors":"Praveen Kumar, Alexander Fell, Sachin Mathur","doi":"10.1109/SOCC.2017.8226010","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226010","url":null,"abstract":"Achieving optimal floor-plans during the physical synthesis flow is an iterative and resource intensive process and its quality has a significant impact on subsequent synthesis stages in terms of runtime and quality of results. This problem intensifies due the abundance of macros in advance technology nodes which poses challenges in the physical design flow, especially in the floor-plan stage. It has resulted in an excessive number of channels among macros that need to be spaced carefully and optimized as they consume placement and routing resources. The work presented here is two-fold: First, a tool is introduced for automatic channel space adjustment. Second, the impact of channel space minimization on the quality of results along with runtimes are investigated. Experimental results for two complex partitions of a taped out design, Design-A and Design-B, each with 3M instances including 225 and 205 macros respectively, are presented. The results indicate an existence of an optimum channel spacing in which a 35% and 124% reduction in turn-around-time is observed with same or better quality of results, when compared to the taped out version of the same.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Wednesday keynote I: FDSOI and FINFET for SoC developments 周三主题演讲1:SoC发展中的FDSOI和FINFET

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225991

G. Teepe

引用次数: 0

Selectable grained reconfigurable architecture (SGRA) and its design automation 可选择粒度的可重构体系结构(SGRA)及其设计自动化

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226035

Ryosuke Koike, Takashi Imagawa, R. Y. Omaki, H. Ochi

引用次数: 0

Application of machine learning methods in post-silicon yield improvement 机器学习方法在后硅良率提高中的应用

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226049

B. Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann

引用次数: 4

Propelling breakthrough embedded microprocessors by means of integrated photonics 利用集成光子学推动嵌入式微处理器的突破

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225981

D. Bertozzi, S. Rumley

{"title":"Propelling breakthrough embedded microprocessors by means of integrated photonics","authors":"D. Bertozzi, S. Rumley","doi":"10.1109/SOCC.2017.8225981","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225981","url":null,"abstract":"The tutorial aims to address electrical communications link limitations by developing chipscale, integrated photonic technology to enable seamless intrachip and off-chip photonic communications that provide the required bandwidth with low energy/bit. The emerging technology will exploit wavelength division multiplexing (WDM), allowing much higher bandwidth capacity per link, which is imperative to meeting the communication needs of future microprocessors. Such a capability would propel the microprocessor onto a new performance trajectory and impact the actual runtime performance of relevant computing tasks for power-starved embedded applications and supercomputing. The challenges in realizing optical interconnect technology are developing CMOS and DRAM-compatible photonic links that are spectrally broad, operate at high bit-rates with very low power dissipation, and are tightly integrated with electronic drivers. Ultimately, the goal of this tutorial is to demonstrate photonic technologies that can be integrated within embedded microprocessors and enable seamless, energy-efficient, high-capacity communications within and between the microprocessor and DRAM. It is envisioned that optical interconnect technology will be especially useful for those platforms where extreme performance coupled with low size, weight, and power is a necessity (e.g. UAVs, and satellites).","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115172435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration Auto-SI:具有运行时循环检测和加速的自适应可重构处理器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226027

T. Harbaum, C. Schade, Marvin Damschen, Carsten Tradowsky, L. Bauer, J. Henkel, J. Becker

引用次数: 3

A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects 一个0.36pJ/bit, 17Gbps的45纳米CMOS OOK接收器，用于芯片间和芯片内无线互连

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226023

Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, A. Ganguly

引用次数: 12

System-level simulator for process variation influenced synchronous and asynchronous NoCs 过程变化影响同步和异步noc的系统级模拟器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226065

S. Muhammad, A. El-Moursy, M. El-Moursy, H. Hamed

{"title":"System-level simulator for process variation influenced synchronous and asynchronous NoCs","authors":"S. Muhammad, A. El-Moursy, M. El-Moursy, H. Hamed","doi":"10.1109/SOCC.2017.8226065","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226065","url":null,"abstract":"System-Level simulator is proposed to determine the ability of synchronous and asynchronous NoCs to alleviate the process variation effect. Throughput variation and different delay components variation are provided by the newly developed framework. System-Level simulation shows similarities with circuit-level simulation in terms of behavior and performance variation trend when moving from one technology node to another. Clock skew significantly degrades synchronous NoCs performance. Clock skew is more obvious with process variation. Despite the handshaking overhead, asynchronous NoC may be more immune to process variation than synchronous networks. PV-aware routing algorithm reduces the performance degradation to 8.3% and 11.4% for 45nm and 32nm asynchronous NoCs respectively. Using different traffic workloads and PV-unaware routing algorithm, synchronous networks lose on average 17.7% and 27.8% of nominal throughput for 45nm and 32nm technologies, respectively due to process variation. Whereas, asynchronous NoC throughput degradation is about 7.4% and 11.5% for 45nm and 32nm, respectively. In addition to technology scaling, NoC scaling also affects the throughput degradation. 256-core NoC shows the highest throughput degradation of 16% and 22% for asynchronous NoC for 45nm and 32nm technologies respectively.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122911871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC ARM TrustZone扩展在异构SoC中的安全性评估

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226018

E. M. Benhani, Cédric Marchand, A. Aubert, L. Bossuet

引用次数: 22