2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献

Content-aware line-based power modeling methodology for image signal processor 基于内容感知线的图像信号处理器功率建模方法

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-12-18 DOI: 10.1109/SOCC.2017.8226075

Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen

{"title":"Content-aware line-based power modeling methodology for image signal processor","authors":"Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen","doi":"10.1109/SOCC.2017.8226075","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226075","url":null,"abstract":"Early power modeling and analysis using electronic system-level methodology enables designers to explore energy saving opportunities more efficiently at a higher abstraction level. However, power modeling for third party IPs are challenging due to the limited observability and unknown architecture details. To model the data dependency for blackbox IPs, several works rely on adopting Hamming distance of input data to approximate the switching activity, which might be not enough for modeling complex IPs such as image signal processors (ISP). This work introduces a content-aware line-based power modeling method for ISP by training an associated energy table. To effectively estimate ISP energy consumption which involves many two-dimensional data processing, this work presents a direct energy-mapping strategy using pixel luminance and gradient. Moreover, an iterative box-constrained least-squares estimation and its associated constraint refinement scheme is proposed to increase the robustness of the trained energy table even with limited training data. Simulation results show that the proposed method can reduce at least 11.54% of average error and 55.52% of max error as compared to the existing content-blind power model.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"22 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125782386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Designing bio-inspired autonomous error-tolerant massively parallel computing architectures 设计仿生自主容错大规模并行计算架构

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226057

Lizheng Liu, Yi Jin, Yi Liu, Ning Ma, Z. Zou, Lirong Zheng

{"title":"Designing bio-inspired autonomous error-tolerant massively parallel computing architectures","authors":"Lizheng Liu, Yi Jin, Yi Liu, Ning Ma, Z. Zou, Lirong Zheng","doi":"10.1109/SOCC.2017.8226057","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226057","url":null,"abstract":"The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative evolutions strategy is studied to handle unrecoverable errors. A circuit backup mechanism is proposed for generating an effective way by setting the routing rules to bypass the failed link or node to achieve fault tolerance capabilities. The print circuit board (PCB) prototype is designed and implemented based on a reconfigurable and scalable control-centric dual-core embedded processor (ReSC). Different testing programs associating fault-detection or self-backup schemes and routing algorithms are explored in the platform. Experimental results show that error perceptron can detect the faults and reassign the task for other remaining free and healthy AET cell through Network-on-chip (NoC) when faults occur at the AET cell. The system can complete error recovery within 3 seconds, the paper shows the error-tolerant capability of the proposed architecture is better than the conventional multi-modular redundant system.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"392 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126748216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique 一种采用自适应米勒补偿技术的恒带宽开关电容可编程增益放大器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226051

Hyunjong Kim, Yujin Park, Han Yang, Suhwan Kim

引用次数: 3

Approximate compressed sensing for hardware-efficient image compression 用于硬件高效图像压缩的近似压缩感知

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226074

S. Kadiyala, V. Pudi, S. Lam

引用次数: 3

A 590MDE/s semi-global matching processor with lossless data compression 具有无损数据压缩功能的590MDE/s半全局匹配处理器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225998

Kyeongryeol Bong, K. Lee, H. Yoo

引用次数: 1

A novel power reduction technique using wire multiplexing 一种采用线复用的新型功率降低技术

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226026

Mostafa Said, Hossam Hassan, Hyungwon Kim, Mostafa Khamis

引用次数: 2

FPGA-based CNN inference accelerator synthesized from multi-threaded C software 基于fpga的CNN推理加速器，由多线程C软件合成

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226056

Jin Hee Kim, Brett Grady, Ruolong Lian, J. Brothers, J. Anderson

引用次数: 38

BlooXY: On a non-invasive blood monitor for the IoT context 在物联网环境下的非侵入性血液监测仪上

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226000

Daniel Flórez, Martha Johanna Sepúlveda

引用次数: 5

Region based cache coherence for tiled MPSoCs 基于区域的平铺mpsoc缓存一致性

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226059

A. Srivatsa, Sven Rheindt, Thomas Wild, A. Herkersdorf

{"title":"Region based cache coherence for tiled MPSoCs","authors":"A. Srivatsa, Sven Rheindt, Thomas Wild, A. Herkersdorf","doi":"10.1109/SOCC.2017.8226059","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226059","url":null,"abstract":"The need for faster and more energy efficient computing has led us to the multicore era with distributed shared memory hierarchies. The primary goal is to distribute parallel tasks onto multiple processing elements to collectively achieve shorter execution times at lower frequencies and supply voltages when compared to a single-core architecture. Major challenges of this approach are how to achieve local, low latency memory accesses and low overheads for coherence and synchronization management. We believe that enabling global coherence in tiled many-core architectures does not scale in a cost efficient manner and isn't even required for applications with limited degrees of parallelism. In this paper, we propose a novel region based cache coherence scheme, where coherence is provided by hardware directories within a flexibly sized but confined set of compute and memory tiles. We also show that data placement and task mapping have a huge impact on the application performance, and hence should be considered in conjunction with region based coherence. The approach is evaluated by means of a high level simulation model using workloads from PARSEC. Experiments demonstrate that our region based approach with multiple compute tiles increases performance by a factor of up to 2.5 compared to a single tile structure with nominally identical computing and memory resources. Thus the independent local memory accesses, which are effectively increasing the memory bandwidth, usually outweigh the penalties of inter-tile remote memory accesses. Our approach also reduces the directory structures significantly compared to traditional schemes, making it scalable for large MPSoCs (eg. by 41.4% for a 16 tile system with 4 tiles per region). Considering data-to-task-placement, our investigations show that it can lead to performance variations up to a factor of 12.7.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125973391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Securing FPGA SoC configurations independent of their manufacturers 确保FPGA SoC配置独立于其制造商

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226019

Nisha Jacob, J. Wittmann, Johann Heyszl, Robert Hesselbarth, F. Wilde, Michael Pehl, G. Sigl, K. Fischer

{"title":"Securing FPGA SoC configurations independent of their manufacturers","authors":"Nisha Jacob, J. Wittmann, Johann Heyszl, Robert Hesselbarth, F. Wilde, Michael Pehl, G. Sigl, K. Fischer","doi":"10.1109/SOCC.2017.8226019","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226019","url":null,"abstract":"System-on-Chips which include FPGAs are important platforms for critical applications since they provide significant software performance through multi-core CPUs as well as high versatility through integrated FPGAs. Those integrated FP-GAs allow to update the programmable hardware functionality, e.g. to include new communication interfaces or to update cryptographic accelerators during the life-time of devices. Updating software as well as hardware configuration is required for critical applications such as e.g. industrial control devices or vehicles with long life-times. Such updates must be authenticated and possibly encrypted. One way to achieve this is to rely on static FPGA manufacturer-provided cryptography and respective master keys. However, in this contribution, we show how to retrofit Xilinx Zynq FPGAs with an alternative cryptographic accelerator and how to establish device-individual keys using Physical Unclonable Function (PUF) technology. These two key aspects reduce the required trust in manufacturer-provided security features while increasing the security by binding configurations to a specific device.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15