2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献_第2页

Hybrid multi-swarm optimization based NoC synthesis 基于混合多群优化的NoC合成

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226008

Muhammad Obaidullah, G. Khan

{"title":"Hybrid multi-swarm optimization based NoC synthesis","authors":"Muhammad Obaidullah, G. Khan","doi":"10.1109/SOCC.2017.8226008","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226008","url":null,"abstract":"Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to cross-points and produce a best NoC configuration with minimum average communication traffic, power consumption and chip area. We use pre-synthesized network components data to estimate power and chip area of the NoC. NoC configuration and mapping problem belongs to NP-hard complexity set, therefore we propose a hybrid scheme of swarm optimization that combines Tabu-search, force-directed swapping, sub-swarms, and Discrete Particle Swarm Optimization (DPSO). The main goal of the optimization is to configure the NoC such that the total NoC latency, power consumption, and area occupied are minimal. DPSO is used as the main optimization scheme and modified so that each particle move is also influenced by a force derived from the NoC traffic matrix. The methodology is tested for some multimedia application core graphs as well as large network of randomly generated cores. It is determined that on average our hybrid technique required less number of iterations and time to reach an optimal solution when compared with existing NoC synthesis algorithms.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123077202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interface 用于集成电容传感器接口的13.5位1.6 mW三阶CT ΣΔ ADC

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226003

Javed S. Gaggatur, Gaurab Banerjee

引用次数: 1

Investigation of diode triggered silicon control rectifier turn-on time during ESD events ESD事件中二极管触发硅控整流器导通时间的研究

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226031

Ahmed Y. Ginawi, R. Gauthier, T. Xia

引用次数: 0

A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs 用于人工智能soc中低功耗鲁棒深度树搜索的1.41mW片上/片外混合换位表

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226024

Dongjoo Shin, Youchang Kim, H. Yoo

引用次数: 1

Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems — Optimization of technology — Architecture — Design 周三主题演讲II:汽车驾驶舱、工业人机界面和物联网系统的先进技术-技术优化-架构-设计

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225992

Ron Martino

{"title":"Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems — Optimization of technology — Architecture — Design","authors":"Ron Martino","doi":"10.1109/SOCC.2017.8225992","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225992","url":null,"abstract":"Electronic innovation is becoming increasingly important in the evolution of our society. Noble goals of extending lives with improved medical capabilities, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges. New system solutions are requiring the integration of disparate functional blocks, high levels of optimization for energy efficiency and scaling across a large dynamic range of performance. A central focus in this evolution is the enhancements to the human-machine-interface (HMI), enabling seamless interactions between humans and machines. Multimedia applications processors are playing a critical role in introducing solutions with multisensory capabilities such as natural language recognition, vision detection and augmentation of reality through enhanced display functionality. We will explore HMI trends in multiple applications and discuss how FD-SOI technology, novel applications processor architectures, integrated circuit module development and system-on-chip integration create safe and secure systems.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125206445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accelerating chip design with machine learning: From pre-silicon to post-silicon

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226046

Cheng Zhuo, Bei Yu, Di Gao

引用次数: 7

Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks 封装内存储栈多芯片系统的高能效无线互连框架

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226077

Md Shahriar Shamim, M. Ahmed, N. Mansoor, A. Ganguly

引用次数: 7

A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHz 一个0.13 CMOS集成电路的电阻抗光谱从1千赫到10千兆赫

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226022

R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío

引用次数: 1

Digital spiking neuron cells for real-time reconfigurable learning networks 用于实时可重构学习网络的数字脉冲神经元细胞

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226029

Haipeng Lin, A. Zjajo, R. V. Leuken

引用次数: 0

Fairness-oriented switch allocation for networks-on-chip 面向公平的片上网络交换机分配

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226066

Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo

{"title":"Fairness-oriented switch allocation for networks-on-chip","authors":"Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo","doi":"10.1109/SOCC.2017.8226066","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226066","url":null,"abstract":"Networks-on-Chip (NoC) is becoming the backbone of modern chip multiprocessor (CMP) systems. However, with the number of integrated cores increasing and the network size scaling up, the network-latency imbalance is becoming an important problem, which seriously influences the performance of the network and system. In this paper, we aim to alleviate this problem by optimizing the design of switch allocation. We propose fairness-oriented switch allocation (FOSA), a novel switch allocation strategy to achieve uniform network latencies. FOSA can improve system performance by achieving remarkable improvement in balancing network latencies. We evaluate the network and system performance of FOSA with synthetic traffics and SPEC CPU2006 benchmarks in a full-system simulator. Compared with the canonical separable switch allocator (Round-Robin) and the recently proposed switch allocator (TS-Router), the experiments with benchmarks show that our approach decreases maximum latency (ML) by 45.6% and 15.1%, respectively, as well as latency standard deviation (LSD) by 13.8% and 3.9%, respectively. Besides this, FOSA improves system throughput by 0.8% over that of TS-Router. Finally, we synthesize FOSA and give an evaluation of the additional consumption of area and power.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0