设计仿生自主容错大规模并行计算架构

Lizheng Liu, Yi Jin, Yi Liu, Ning Ma, Z. Zou, Lirong Zheng
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引用次数: 3

摘要

由许多处理器组成的可扩展和大规模并行计算系统将变得越来越复杂和不可靠。提出了一种基于自主容错(AET)体系结构的仿生容错框架和三种设计原则。设计了就近错误感知机制来检测故障,研究了主动进化策略来处理不可恢复的错误。提出了一种电路备份机制,通过设置路由规则绕过故障链路或节点来产生一种有效的方式,以达到容错的目的。印刷电路板(PCB)原型是基于可重构和可扩展的控制中心双核嵌入式处理器(ReSC)设计和实现的。不同的测试程序关联故障检测或自备份方案和路由算法在平台上进行了探索。实验结果表明,当AET细胞发生故障时,错误感知器可以检测到故障,并通过片上网络(Network-on-chip, NoC)将任务重新分配给其他空闲的健康AET细胞。系统可以在3秒内完成错误恢复,表明该结构的容错能力优于传统的多模块冗余系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Designing bio-inspired autonomous error-tolerant massively parallel computing architectures
The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative evolutions strategy is studied to handle unrecoverable errors. A circuit backup mechanism is proposed for generating an effective way by setting the routing rules to bypass the failed link or node to achieve fault tolerance capabilities. The print circuit board (PCB) prototype is designed and implemented based on a reconfigurable and scalable control-centric dual-core embedded processor (ReSC). Different testing programs associating fault-detection or self-backup schemes and routing algorithms are explored in the platform. Experimental results show that error perceptron can detect the faults and reassign the task for other remaining free and healthy AET cell through Network-on-chip (NoC) when faults occur at the AET cell. The system can complete error recovery within 3 seconds, the paper shows the error-tolerant capability of the proposed architecture is better than the conventional multi-modular redundant system.
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