2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献_第4页

A unified HW/SW system-level simulation framework for next generation wireless system 面向下一代无线系统的统一软硬件系统级仿真框架

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226070

N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi

{"title":"A unified HW/SW system-level simulation framework for next generation wireless system","authors":"N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi","doi":"10.1109/SOCC.2017.8226070","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226070","url":null,"abstract":"Recently, wireless technology experiences a fast growth to meet user demand and push toward the boundary limit of system performance. The simulation and verification framework play important role for accelerating investigation of technology proof of concept, field-trial, and large-scale commercial prototyping. In this paper, we present system-level simulation of heterogeneous model and unified HW/SW framework, particularly for next generation wireless system. The proposed framework includes a unified HW/SW co-evaluation methodology, the flexible HW/SW architecture, and fast HW/SW co-evaluation. The co-evaluation is carried out by employing hardware-in-the loop scheme that covers various abstraction level of simulation, from algorithm-level into physical-level simulation, with respect to system level simulation. The proposed co-verification framework allows a comprehensive system evaluation for a wireless system, involving various system parameters, hardware impairments, different channel conditions and cross-layer evaluations with fast run-time evaluations. Additionally, we also show an application example of multi-user wireless communication system and its experimental evaluations.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A decomposition-based system level synthesis method for heterogeneous multiprocessor architectures 基于分解的异构多处理器体系结构系统级综合方法

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226082

György Rácz, P. Arató

{"title":"A decomposition-based system level synthesis method for heterogeneous multiprocessor architectures","authors":"György Rácz, P. Arató","doi":"10.1109/SOCC.2017.8226082","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226082","url":null,"abstract":"Multiprocessing can be considered the most characteristic common property of complex digital systems. Due to the more and more complex tasks to be solved for fulfilling often conflicting requirements (cost, speed, energy and communication efficiency, pipelining, parallelism, the number of component processors, etc.), the so called heterogeneous multiprocessor architectures (HMPA) have become unavoidable. The component processors of such systems may be not only general purpose CPUs or cores, but also DSPs, GPUs, FPGAs and other custom hardware components as well. The hierarchy of the component processors and the data transfer organization between them are strongly determined by the task to be solved and by the priority order of the requirements to be fulfilled. For each component processor of HMPAs, a subtask must be defined based on the requirements and their priority orders. The definition of the subtasks, i.e. the decomposition of the task influences strongly the cost and performance of the whole system. Therefore, comparing and evaluating the effects of different task decompositions performed by applying systematic algorithms may help the designer to approach the optimal decisions in the system level synthesis phase. For this purpose, the paper presents a novel method based on combining the decomposition and the modified high level synthesis algorithms. The application of the method is illustrated on redesigning and evaluating in some versions of a high performance embedded multiprocessing system.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"505 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Optimizing the heterogeneous network on-chip design in manycore architectures 优化多核架构下的异构网络片上设计

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226033

T. Le, R. Ning, Dan Zhao, Hongyi Wu, M. Bayoumi

引用次数: 9

A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications 一个低功耗，可编程的12位两步sar闪存ADC的信号处理应用

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226004

M. K. Adimulam, K. K. Movva, M. Srinivas

{"title":"A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications","authors":"M. K. Adimulam, K. K. Movva, M. Srinivas","doi":"10.1109/SOCC.2017.8226004","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226004","url":null,"abstract":"This paper presents a low power programmable 12-bit Two Step successive approximation register (SAR) — Flash analog-to-digital converter architecture for communication and bio-potential signal processing applications. The proposed ADC consists of two identical 6-bit SAR-Flash analog-to-digital converter (ADC) stages combined with a pipelined inter-stage gain amplifier to improve performance, reduce area, and power consumption. The 6-bit SAR-Flash ADC stage consists of low power and high performance 3-bit SAR ADC and 3-bit flash ADC. The proposed ADC architecture results are compared with recent conventional SAR ADCs and hybrid ADCs at different sampling frequencies. The ADC is designed in 90nm standard CMOS process occupies 0.1225 mm2 area. The performance parameters of the proposed ADC design are found to be differential nonlinearity (DNL) of ±0.28 LSB, integral non-linearity (INL) of ±0.52 LSB, signal-to-noise-and-distortion ratio (SNDR) of 67.4 dB, spurious-free dynamic range (SFDR) of 79.6 dB, and effective number of bits (ENOB) of 10.9 bits with input frequency of 15 MHz @ 200 MS/s sampling frequency at 1.0 V supply voltage. The power consumption of the ADC at lower sampling frequency at 500 KS/s is 1.47 pW and at 200 MS/s it is 1.35 mW.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design automation for Labs-on-Chip: A new “playground” for SoC designers 芯片实验室的设计自动化:SoC设计人员的新“游乐场”

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225986

R. Wille, Bing Li

引用次数: 0

Realization of buck converter with adaptive variable-frequency control 自适应变频控制降压变换器的实现

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226042

Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng

引用次数: 2

Supercapacitor-based embedded hybrid solar/wind harvesting system architectures 基于超级电容器的嵌入式混合太阳能/风能收集系统架构

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226043

M. Habibzadeh, Moeen Hassanalieragh, T. Soyata, Gaurav Sharma

引用次数: 11

Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs 热模拟辅助安全soc的98mJ集成高侧和低侧驱动器设计

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226036

Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel

{"title":"Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs","authors":"Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel","doi":"10.1109/SOCC.2017.8226036","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226036","url":null,"abstract":"Power Semiconductor devices used for high voltage, high current applications dissipate lot of power thereby rapidly increasing their junction temperature to levels beyond which no SPICE (Simulation Program with Integrated Circuit Emphasis) models exist. In this paper, the design of an integrated four channel squib driver SOC (System on Chip) with four High Side (HS) drivers and four Low Side (LS) drivers is presented. 98mJ energy limited current regulating High Side (HS) driver needs the temperature information from the electro-thermal simulators like FloTHERM during the design to ensure that the powerFET operates within the thermal SOA (Safe Operating Area) without area penalty. Despite SPICE model restrictions to 200°C, this paper explains how the current regulation loop architecture is chosen to operate at peak temperatures of 400°C. The Thermal simulation results aid in the optimization of the layout of the gate-driver. Apart from the robust design, additional design measures to prevent inadvertent turn ON of the FETs and reverse protection for safety are discussed. This circuit was successfully implemented in a 40V, 0.35pm, BiCMOS process on a 4 channel airbag squib driver IC.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Introduction to hardware-oriented security for MPSoCs 介绍面向硬件的mpsoc安全性

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226017

I. Polian, F. Regazzoni, Martha Johanna Sepúlveda

引用次数: 1

Time sensitive networks for industry 4.0 工业4.0的时间敏感网络

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225980

T. Leyrer

引用次数: 0