2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献_第5页

Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain 带有专用进位链的混合粒度可重构体系结构的布局算法

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226012

Takashi Imagawa, Koki Honda, H. Ochi

{"title":"Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain","authors":"Takashi Imagawa, Koki Honda, H. Ochi","doi":"10.1109/SOCC.2017.8226012","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226012","url":null,"abstract":"This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this mixed-grained architecture is expected to enhance the performance of the implemented application circuit, placement becomes problematic because of the inherent placement constraints. For example, some logic blocks have many connections to others and constraints such as these cause simple pair-swap-based SA to converge to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the versatile place and route (VPR) approach. The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Multifractal on-chip traffic generation under TLM TLM下的多重分形片上流量生成

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226009

J. B. Filho, J. Wang

引用次数: 1

The memory challenge in computing systems: A survey 计算机系统中的内存挑战:综述

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226062

N. Wehn

引用次数: 0

A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy model 基于EPI能量模型的商用处理器和soc能量精度权衡研究

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226072

Jeremy Schlachter, M. Fagan, K. Palem, C. Enz

{"title":"A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy model","authors":"Jeremy Schlachter, M. Fagan, K. Palem, C. Enz","doi":"10.1109/SOCC.2017.8226072","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226072","url":null,"abstract":"Energy-efficiency is a critical concern for many computing systems. With Moore's law showing its limits, new hardware design and programming techniques emerge to pursue energy scaling. Among these, approximate computing is certainly the most popular in current works. It has been shown that reducing precision using software techniques can show significant energy savings on commercially available processors. In this paper, an energy model based on Energy Per Instruction (EPI) has been built in order to understand which mechanisms enable those savings. EPIs of various instructions have been measured and data movement has been identified as being the major consumer. The energy model has been evaluated on a computationally intensive Newton method for solving nonlinear equations using double-precision and single-precision floating-point data types. For all the cases, the model predicts the consumption with less than 10 % error. The energy breakdown reveals that arithmetic operations consume less than 6 % of the total energy and that savings are mainly achieved by reducing the amount of data transferred between registers, cache and main memory. With these conclusions, implementing approximate arithmetic circuits in this type of architecture would have a very limited impact on the consumption. It is however shown that specialized hardware implemented on an FPGA interconnected with a processing system can lead to an additional 20 % energy savings on the Newton method using the same single-precision data type.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Providing throughput guarantees in mixed-criticality networks-on-chip 在片上混合临界网络中提供吞吐量保证

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226064

Sebastian Tobuschat, R. Ernst

{"title":"Providing throughput guarantees in mixed-criticality networks-on-chip","authors":"Sebastian Tobuschat, R. Ernst","doi":"10.1109/SOCC.2017.8226064","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226064","url":null,"abstract":"Future mixed-criticality systems must handle a growing variety of traffic requirements, ranging from safety-critical real-time traffic to bursty latency-sensitive best-effort traffic. Additionally, safety standards (e.g. ISO 26262) require sufficient independence among different criticality levels for mixed-criticality systems. Networks-on-Chip (NoCs), as a scalable and modular interconnect, are used as a promising solution for such systems. Hence, a NoC must provide performance isolation for safety-critical traffic and low latency for best-effort traffic at the same time. This paper presents a run-time configurable NoC design enabling throughput guarantees for selected traffic streams with reduced adverse impact on the performance of best-effort traffic. In contrast to existing approaches, we prioritize best-effort over guaranteed throughput traffic and only switch priorities when required, providing sufficient performance isolation among different criticality levels. We show that the overhead implementing our approach is affordable. And through an experimental evaluation, we show that the approach reduces the adverse effects through strict prioritization on best-effort applications.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Power and area evaluation of a fault-tolerant network-on-chip 片上容错网络的功率和面积评估

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226034

Thawra Kadeed, Eberle A. Rambo, R. Ernst

引用次数: 5

Lithography hotspot detection: From shallow to deep learning 光刻热点检测:从浅层到深度学习

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226047

Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young

引用次数: 35

Efficient virtual channel allocator for NoC router micro-architecture NoC路由器微体系结构的高效虚拟信道分配器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226030

Y. Lan, V. Muthukumar

引用次数: 3

Reliability for IoT and automotive markets 物联网和汽车市场的可靠性

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225984

Subhadeep Ghosh, Scott Martin, Shane Stelmach

引用次数: 1

A random access analog memory with master-slave structure for implementing hexadecimal logic 具有主从结构的随机存取模拟存储器，用于实现十六进制逻辑

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225995

Renyuan Zhang, M. Kaneko

{"title":"A random access analog memory with master-slave structure for implementing hexadecimal logic","authors":"Renyuan Zhang, M. Kaneko","doi":"10.1109/SOCC.2017.8225995","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225995","url":null,"abstract":"A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is proposed with eighteen transistors, which is 28% of four pieces of binary master-slave flipflop. The hexadecimal voltage values are stored on the floating gate; and the read-out operations are executed by a comparator to protect the stored voltage. This comparator is powered only during the read-out operation. In this manner, the static power is eliminated. By using the proposed timing control mode, the master and slave stages are organized for hexadecimal sequential logic. As a demonstration, a sixteen-counter is designed on the basis of proposed analog memory without combinational logic circuits, in which the number of devices is reduced in contrast of binary approaches. From the circuit simulation results, the designed circuits maintain the hexadecimal values and execute hexadecimal functions correctly.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134346213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0