2017 30th IEEE International System-on-Chip Conference (SOCC)最新文献_第6页

Virtual white board: Leveraging investments in interface based design and executable specification 虚拟白板:利用对基于接口的设计和可执行规范的投资

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226037

Todd Hiers, Chunhua Hu, B. Karguth, Chuck Fuoco

{"title":"Virtual white board: Leveraging investments in interface based design and executable specification","authors":"Todd Hiers, Chunhua Hu, B. Karguth, Chuck Fuoco","doi":"10.1109/SOCC.2017.8226037","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226037","url":null,"abstract":"Interface-based design methodologies and tools using machine-readable metadata have been in use for many years; however, a lot of manual effort is still needed to gather module information, especially when the SoC and modules are being co-designed. It is a time-consuming and error prone challenge made more difficult by increasing SoC complexity. Various efforts to address these issues with document-based “executable specifications” met with only modest success. By committing fully to an architecture-specific web-based executable specification tool, the metadata available in the ecosystem could be leveraged to greatly improve the specification-to-design process. This paper presents a case study on a unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams by building and using an architecture-aware tool to comprehend the SoC constructs. A modern web-based framework instead of a standalone tool gave built-in collaboration capabilities and an easy way to visually represent and manipulate data. Various architectural rules about these connections can be enforced. Connection fabrics (e.g. NoC) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design easily due to the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as reference for design teams tasked with implementation. Reports and automated software generation satisfy the needs of the design verification and software teams. Overall team productivity is greatly enhanced — infrastructure is produced much more quickly with fewer engineers needed. The shorter revision cycle also speeds and simplifies functional and performance testing feedback loops.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132728997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array 光可重构门阵列上高速擦洗的辐射耐受性论证

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226014

Takumi Fujimori, Minoru Watanabe

引用次数: 0

The importance of benchmarking for charge-based and beyond CMOS devices 基准测试对基于电荷和超越CMOS器件的重要性

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225987

A. Marshall, N. Sharma

引用次数: 0

Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS 在14nm FinFET CMOS中具有快速上电和0.82 pJ/bit的28 Gb/s的光电模拟前端

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226052

Jan Plíva, M. Khafaji, László Szilágyi, R. Henker, F. Ellinger

{"title":"Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS","authors":"Jan Plíva, M. Khafaji, László Szilágyi, R. Henker, F. Ellinger","doi":"10.1109/SOCC.2017.8226052","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226052","url":null,"abstract":"This paper presents the design and the opto-electrical measurements of a power-efficient receiver analog front-end (AFE) for optical communication with standby mode and rapid recovery time below 10 ns. The circuit was designed and fabricated in advanced 14 nm FinFET CMOS with a small area of 0.0159mm2. The AFE consumes 22.6mW power, thus achieving a power efficiency of 0.82 pJ/bit. Furthermore, a power saving standby mode is supported which is a feature not commonly available in state-of-the-art designs. During the powersaving mode, the limiting amplifier (LA) is shut down resulting in power consumption reduction of 50 % down to 11.4 mW. A recovery time from standby mode amounting to 8.2 ns was measured, thus making the front-end suitable for future standard burst mode operation. For measurements, a multi-chip assembly with a photo diode in 850 nm band was fabricated and the performance was measured using an optical probe. A bit error rate (BER) of 10−12 was achieved for a data rate of 28 Gb/s with an optical sensitivity of −3.5 dBm optical modulation amplitude (OMA).","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133204027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A low complexity UWB PHY baseband transceiver for IEEE 802.15.6 WBAN ieee802.15.6 WBAN的低复杂度UWB PHY基带收发器

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226054

A. Bondok, A. M. El-Mohandes, A. Shalaby, M. Sayed

引用次数: 3

LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226058

Hantao Huang, Leibin Ni, Hao Yu

引用次数: 7

IBM Q — Introduction into quantum computing with live demo IBM Q -介绍量子计算与现场演示

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225985

A. Frisch

引用次数: 2

Low power circuit optimization for IoT 物联网低功耗电路优化

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225982

M. Pronath

{"title":"Low power circuit optimization for IoT","authors":"M. Pronath","doi":"10.1109/SOCC.2017.8225982","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225982","url":null,"abstract":"Designing circuits for enhanced IoT (“Internet of Things”) applications is one of the current growth driver for the electronics industry. Optimizing such circuits for lowest power consumption while maximize functionality and performance is key for successful implementation of such circuits in the IoT systems. IoT devices are diverse in nature but are typically constrained by limited power availability, limited area budget and the need for modularity of design. The burden of ultra-low-power budget unfortunately doesn't necessarily mean that other performance requirements are relaxed. The tutorial is therefore geared towards designers of IoT devices including sensors, MEMS, mobile devices, medical sensors, wireless communication devices, near field communication devices, energy harvesting designs, mobile devices, and wireless communication devices. It will focus on how automated circuit sizing and tuning methodologies can be used to enhance existing design expertise to reduce power consumption while trade-off with other circuit performances. Additionally it will be shown how features like circuit sensitivity analysis can be used for confirming design hypotheses. Using such a verification and optimization environment can help systematically and fully explore design's operating, design and statistical design space.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114809363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

FDSOI design experience and recommendations FDSOI设计经验与建议

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8225983

Herbert Preuthen, Jurgen Dirks

引用次数: 0

Router-level performance driven dynamic management in hierarchical networks-on-chip 分层片上网络中路由器级性能驱动的动态管理

2017 30th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2017-09-01 DOI: 10.1109/SOCC.2017.8226067

Mingmin Bai, Dan Zhao, M. Bayoumi

{"title":"Router-level performance driven dynamic management in hierarchical networks-on-chip","authors":"Mingmin Bai, Dan Zhao, M. Bayoumi","doi":"10.1109/SOCC.2017.8226067","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226067","url":null,"abstract":"When on-chip interconnection network scales to integrate more processing elements, the average end-to-end latency is highly increased due to long average hop distance. Though it has been discovered that, almost of the communication in large scale networks is between nodes in a short range, it revealed that the small portion of data delivery between distant nodes consumes or occupies most of the network bandwidth. Hierarchical NoCs caters an attractive solution to resolve the distant data transmission problem by taking advantage of the network hierarchy. However, it brings about new sever congestion challenge because of uneven traffic distribution among hierarchy. In previous work, we performed a detouring scheme on a layered hierarchical NoC. When congestion is formed on the access link to adjacent hierarchical layer, the detouring scheme seeks and reroutes the packets to an nearby node to access the next adjacent network layer. It revealed that the links, which bridges the packets up to higher layers, are more essential for distributing the traffic and avoiding congestion between hierarchy levels. In this paper, we proposed dynamic schemes to solve the congestion problem introduced by region-based hierarchical routing on a hierarchical NoC. The results exposed that the dynamic approaches are efficient to manage the congestion under heavier long range traffic load, yielding significant average network latency reduction and throughput increment under mixed synthetic traffic patterns.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131183127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3