A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects

Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, A. Ganguly
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引用次数: 12

Abstract

Wireless interconnects are capable of establishing energy-efficient intra and inter-chip data communications. This paper introduces a circuit level design of an energy-efficient millimeter-wave (mm-wave) non-coherent on-off keying (OOK) receiver suitable for such wireless interconnects in 45-nm CMOS process. The receiver consists of a simple two-stage common source structure based Low Noise Amplifier (LNA) and a source degenerated differential Envelope Detector (ED) followed by a Base Band (BB) amplifier stage. Operating at 60GHz, the proposed OOK receiver consumes only 6.1mW DC power from a 1V supply while providing a data rate of 17Gbps and a bit-energy efficiency of 0.36 pJ/bit.
一个0.36pJ/bit, 17Gbps的45纳米CMOS OOK接收器,用于芯片间和芯片内无线互连
无线互连能够建立节能的芯片内部和芯片之间的数据通信。本文介绍了一种适用于45纳米CMOS工艺无线互连的高能效毫米波非相干键控(OOK)接收机的电路级设计。该接收机由一个简单的基于两级共源结构的低噪声放大器(LNA)和一个源退化差分包络检测器(ED)以及一个基带(BB)放大器级组成。该OOK接收器工作在60GHz时,在1V电源下仅消耗6.1mW直流功率,同时提供17Gbps的数据速率和0.36 pJ/bit的比特能量效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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