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2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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MWSCAS 2018 Author Index MWSCAS 2018作者索引
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/mwscas.2018.8624094
{"title":"MWSCAS 2018 Author Index","authors":"","doi":"10.1109/mwscas.2018.8624094","DOIUrl":"https://doi.org/10.1109/mwscas.2018.8624094","url":null,"abstract":"","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133484756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Coupled Schmitt Trigger Oscillator Neural Network for Pattern Recognition Applications 模式识别中的耦合Schmitt触发振荡器神经网络
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624010
Ting Zhang, M. Haider, J. I. D. Alexander, Y. Massoud
{"title":"A Coupled Schmitt Trigger Oscillator Neural Network for Pattern Recognition Applications","authors":"Ting Zhang, M. Haider, J. I. D. Alexander, Y. Massoud","doi":"10.1109/MWSCAS.2018.8624010","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624010","url":null,"abstract":"This paper demonstrates a coupled Schmitt trigger oscillator based oscillator neural network (SMT-ONN) for pattern recognition applications. Unlike previous ONN models, the SMT-ONN can be easily realized in both hardware and software levels. A mathematical model of the Schmitt Trigger Oscillator as well as the corresponding CMOS circuit are presented to validate the mathematical model. The SMT-ONN can realize the pattern recognition task by considering the convergence time and frequency as the recognition indicators. A Kuramoto model based frequency synchronization approach is utilized, and simulation results indicate less than 160 ms convergence time and close frequency match for a simplified pattern recognition application.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133327949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers 受感染的片上网络路由器的路由感知和运行时检测
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623972
Luka Daoud, N. Rafla
{"title":"Routing Aware and Runtime Detection for Infected Network-on-Chip Routers","authors":"Luka Daoud, N. Rafla","doi":"10.1109/MWSCAS.2018.8623972","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623972","url":null,"abstract":"Network-on-Chip (NoC) architecture is the communication heart of the processing cores in Multiprocessors System-on-Chip (MPSoC), where messages are routed from a source to a destination through intermediate nodes. Therefore, NoC has become a target to security attacks. By experiencing outsourcing design, NoC can be infected with a malicious Hardware Trojans (HTs) which potentially degrade the system performance or leave a backdoor for secret key leaking. In this paper, we propose a HT model that applies a denial of service attack by misrouting the packets, which causes deadlock and consequently degrading the NoC performance. We present a secure routing algorithm that provides a runtime HT detection and avoiding scheme. Results show that our proposed model has negligible overhead in area and power, 0.4% and 0.6%, respectively.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Cascaded Thermometer-Coded Current-Steering Digital-to-Analog Converter 级联温度计编码电流转向数模转换器
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624088
N. Lilic, Peter Speer, H. Zimmermann
{"title":"A Cascaded Thermometer-Coded Current-Steering Digital-to-Analog Converter","authors":"N. Lilic, Peter Speer, H. Zimmermann","doi":"10.1109/MWSCAS.2018.8624088","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624088","url":null,"abstract":"A fully thermometer-coded cascaded current-steering digital-to-analog converter (DAC) is reported in this paper. The described solution is implemented and simulated as a 7-bit DAC. The circuit achieves a $|Dlmathrm{V}L|lt 0.9^{*}mathrm{L}mathrm{S}mathrm{B}$ for extracted view Monte Carlo simulations, temperatures in the range between $-40^{0}mathrm{C}$: $125^{0}mathrm{C}$ and voltage supply in the range 2. 5V: 3.3V. In the 55nm high-voltage CMOS technology, 6V devices are used. The total current consumption is $9mu mathrm{A}$ in the supply range from 2.5V to 3. 3.3V.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122961507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Physically Unclonable Function based on Voltage Divider Arrays in Subthreshold Region 基于亚阈值区域分压器阵列的物理不可克隆函数
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624014
Aishwarya Bahudhanam Venkatasubramaniyan, A. Sanyal
{"title":"Physically Unclonable Function based on Voltage Divider Arrays in Subthreshold Region","authors":"Aishwarya Bahudhanam Venkatasubramaniyan, A. Sanyal","doi":"10.1109/MWSCAS.2018.8624014","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624014","url":null,"abstract":"This paper proposes a novel architecture of a simple, low energy silicon physically unclonable function arrays depending on the large random variation of threshold voltage of MOSFETs operating in subthreshold region. The proposed structure is a strong silicon PUF with 260 challenge response pairs and consumes an energy of 0.48pJ/bit. The PUF is simulated in 65nm CMOS technology and has a normalized inter-HD of 0.4982 and intra-HD of 0.0225.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123052315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes 用于多协议服务器的47mW二维睁眼监视器
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623939
Wenhuan Luan, Ting Chen, S. Yuan, Peijie Li, Ziqiang Wang, Xin Lin, Mao Li, Dengjie Wang, Hong Chen
{"title":"A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes","authors":"Wenhuan Luan, Ting Chen, S. Yuan, Peijie Li, Ziqiang Wang, Xin Lin, Mao Li, Dengjie Wang, Hong Chen","doi":"10.1109/MWSCAS.2018.8623939","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623939","url":null,"abstract":"This paper presents an eye opening monitor (EOM) architecture designed for multi-protocol serial link applications, which is operated at the data rate of 1.25-10Gb/s. The proposed two dimensional EOM provides the variable 248 different masks, based on the phase interpolators (PIs) and the digital-to-analog converters (DACs). The horizontal asymmetric masks are also closer to the real eye. The EOM is achieved in 40nm CMOS technology and supplied with 1.1V. The simulated results show that this design can output a frequency corresponding to the bit error rate (BER). The algorithm that is controlled by digital control logic block V_Control and PI_Control can implement traversal of the variable asymmetric sizes of masks. The total power consumption of the EOM is 47 mW at 10Gb/s in this design.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121478034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-Efficient Data Modulation for All-Mechanical ULF/VLF Transmitters 全机械ULF/VLF发射机的高能效数据调制
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623824
Md. Tawhid Bin Tarek, S. Dharmasena, A. Madanayake, Seungdeog Choi, J. Glickstein, Jifu Liang, S. Mandal
{"title":"Power-Efficient Data Modulation for All-Mechanical ULF/VLF Transmitters","authors":"Md. Tawhid Bin Tarek, S. Dharmasena, A. Madanayake, Seungdeog Choi, J. Glickstein, Jifu Liang, S. Mandal","doi":"10.1109/MWSCAS.2018.8623824","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623824","url":null,"abstract":"Miniaturized and power-efficient ULF/VLF (0.330 kHz) transmitters are desirable for underground and undersea wireless communications. Transmitters based on rotating permanently-polarized dipoles are promising for such applications. This paper proposes a power-efficient data modulation scheme for such mechanical transmitters based on continuous-frequency FSK (CF-FSK). Theoretical analysis and simulations show that 8-ary CF-FSK is optimal since it minimizes average mechanical torque for a given bit rate. Model predictive control (MPC) of a permanent magnet (PM) motor is proposed for robust implementation of the data modulation scheme. Preliminary results from an experimental prototype are also presented.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fly-Inspired Edge Detection: Architecture and Reconfigurable Embedded Implementation 受苍蝇启发的边缘检测:体系结构和可重构嵌入式实现
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624039
Oluwakemi N. Adabonyan, D. Llamocca, Brian K. Dean
{"title":"Fly-Inspired Edge Detection: Architecture and Reconfigurable Embedded Implementation","authors":"Oluwakemi N. Adabonyan, D. Llamocca, Brian K. Dean","doi":"10.1109/MWSCAS.2018.8624039","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624039","url":null,"abstract":"This work presents a reconfigurable embedded implementation of a fly-inspired edge detection algorithm that allows for run-time alteration of the numerical format in response to constraints on accuracy and resources. The low-resource, high-performance system can effectively detect edge orientation and location. This work illustrates the advantages of run-time reconfiguration technology for the implementation of fly-inspired vision algorithms whose capabilities can surpass or supplement traditional image processing systems.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115807712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration fpga重构的实时比特流解压缩方案
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624003
Luka Daoud, F. Hussein, N. Rafla
{"title":"Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration","authors":"Luka Daoud, F. Hussein, N. Rafla","doi":"10.1109/MWSCAS.2018.8624003","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624003","url":null,"abstract":"The state-of-the-art FPGAs require massive configuration files seeking on-chip large memory storage. Partial reconfigurable applications demand even more data storage for several additional partial bitstreams. To alleviate the memory storage requirements, bitstream compression techniques are needed. Efficient compression algorithms usually involve high complex hardware decompression circuits. This might increase the FPGA’s (re)configuration time. In run-time reconfigurable applications, the required time of the decompression engine must be minimized. In this paper, we present a design and implementation of a newly developed bitstream decompression algorithm. The decompression circuit was implemented using Xilinx Vivado EDA design suite on a Zynq-based FPGA. While consuming only 118 CLB slices, 0.89% of the fabric, the decompression speed can reach the theoretical maximum reconfiguration frequency of 400 MB/s on 100 MHz clock as verified by hardware implementation. Furthermore, the effect of the FIFO buffer size and DMA configuration parameters on the decompression speed were studied.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116330241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware Accelerated DNA Sequencing 硬件加速DNA测序
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623915
Zhongpan Wu, Karim Hammad, Yunus Dawji, E. Ghafar-Zadeh, S. Magierowski
{"title":"Hardware Accelerated DNA Sequencing","authors":"Zhongpan Wu, Karim Hammad, Yunus Dawji, E. Ghafar-Zadeh, S. Magierowski","doi":"10.1109/MWSCAS.2018.8623915","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623915","url":null,"abstract":"Basecalling is a core function in DNA sequencing. It is responsible for the conversion of measured date to a text representation of the DNA’s molecular make-up. Recent advances in sequencing machinery have greatly accelerated the rate at which DNA data can be gathered using miniaturized platforms. To keep up, the basecalling function requires sub-stantial computing power. To ease this burden we demonstrate an FPGA-based hardware accelerator for basecalling.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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