{"title":"Incremental Delta Sigma Modulation with Dynamic Weighted Integration","authors":"W. Guicquero, A. Verdant, D. Morche","doi":"10.1109/MWSCAS.2018.8623872","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623872","url":null,"abstract":"This paper presents a technique to reduce the required number of cycles to reach a given quantization resolution of conversion performed by incremental $triangle Sigma $ ADCs. Thanks to a specifically designed dynamic weighting of the modulator's coefficients combined with a dedicated digital filter, the OverSampling Ratio (i.e., OSR) can be reduced compared to conventional structures thanks to a more efficient quantization noise shaping. This Dynamic Weighted Integration (DWI) technique is first motivated in the context of a first order modulator supported with a mathematical proof. In the second part, the proposed technique is extended to the specific case of a complex fourth order modulator with four different examples of topology regarding the position of the dynamic weighting.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"59 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116796832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation","authors":"T. Maruyama, M. Hamada, T. Kuroda","doi":"10.1109/MWSCAS.2018.8624078","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624078","url":null,"abstract":"The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117206023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Benjamin Wolff, Bachir Fradj, N. Bélanger, Y. Savaria
{"title":"Extending a CPU Cache for Efficient IPv6 Lookup","authors":"Benjamin Wolff, Bachir Fradj, N. Bélanger, Y. Savaria","doi":"10.1109/MWSCAS.2018.8623871","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623871","url":null,"abstract":"Increasing throughput requirements for Internet routers and growing routing table sizes have emphasized the need for fast and scalable packet forwarding systems. This paper presents a hardware cache-based IPv6 lookup system. Our goal is to study how much performance can be achieved with a lookup system that is implemented by modifying a processor cache. We show by prototyping our system on an FPGA board that our solution provides efficient IPv6 packet forwarding. In particular, the solution’s hardware complexity grows only linearly with table size. Our basic FPGA implementation can support a 1Gb link for minimum sized packets, and an improved implementation, discussed in this paper, could improve this throughput by an order of magnitude. Finally, an ASIC implementation would support 100Gb of bandwidth if there is no other bottleneck in the system.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131061165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analytical Design of Elliptically-Shaped 2D Recursive Filters","authors":"R. Matei","doi":"10.1109/MWSCAS.2018.8624079","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624079","url":null,"abstract":"This paper presents an analytic design technique for 2D IIR filters with elliptical symmetry, which have useful applications in image processing. The design is based on efficient elliptic digital filters, regarded as 1D prototypes, to which specific complex frequency transformations are applied; this allows to obtain directly a factored form of the transfer function for the 2D elliptically-shaped filter. The design procedure uses accurate approximations, but no global optimization algorithm. Finally the 2D filter matrices are obtained. The filter is adjustable, its coefficients depending explicitly on the specified orientation and bandwidth. Another advantage is versatility, since the design need not be resumed each time from the start for various specifications. The designed 2D filters have an accurate elliptical shape with low distortions even close to the frequency plane margins, being efficient, of high selectivity and low order.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131193582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MWSCAS 2018 Committees","authors":"","doi":"10.1109/mwscas.2018.8623877","DOIUrl":"https://doi.org/10.1109/mwscas.2018.8623877","url":null,"abstract":"","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132790492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time Series Generation Using Nonlinear Autoregressive Model Artificial Neural Network Based Nonlinear Autoregressive Model Design for the Generation and Prediction of Lorenz Chaotic System","authors":"Lei Zhang","doi":"10.1109/MWSCAS.2018.8623992","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623992","url":null,"abstract":"This paper presents a Nonlinear Auto-Regressive (NAR) model design for the generation and prediction of Lorenz chaotic system using different Artificial Neural Network (ANN) architectures. Electroencephalogram (EEG) signals captured from brain activities demonstrate chaotic features. In order to theoretically understand brain functionalities, the dynamic chaotic time series outputs of a chaotic system with known system equations can be used to train ANN. And the ANN based NAR model can be used for the simulation and analysis of the chaotic features of brain activities. The ANN architecture design and optimization of the NAR chaotic system model is part of the preliminary research of a multidisciplinary brain research program. The ANN training results of different ANN architectures with 3 to 16 neurons in the hidden layer and 1 to 4 input delays of the NAR model, using training data generated with different step sizes provide important information for the selection of optimal training configuration to optimize the training performance. The research outcome is beneficial for the study of brain activities using EEG.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Group Delay Equalizer Design Using Harmony Search Algorithm","authors":"H. Kwan","doi":"10.1109/MWSCAS.2018.8624034","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624034","url":null,"abstract":"Allpass group delay equalizer design using harmony search algorithm is presented. Elliptic IIR lowpass and bandpass digital filters are first designed to meet given passband and stopband(s) magnitude response specifications. For each of the lowpass and bandpass digital filters, a cascaded allpass digital filter is then designed to equalize the IIR passband group delay such that the normalized group delay error of the combined passband group delay is minimized. The allpass equalizer design results indicate that the approach using harmony search algorithm can achieve slightly improved results as compared to other methods.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128192916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using Mixed DCT and Haar Transforms for Efficient Compression of Car Trajectory Data","authors":"Masoumeh Kalantari Khandani, W. Mikhael","doi":"10.1109/MWSCAS.2018.8623987","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623987","url":null,"abstract":"Data compression is an important component of communication and storage technologies, directly contributing to the efficiency of these systems. Lossy data or signal compression, while not applicable to all applications, usually allows for much higher efficiency. In this paper we propose a method for adopting the concept of mixed-transforms and evaluate it for vehicle trajectory data. In mixed-transform methods, compression residuals from the first representation of a signal are passed to a second transformation stage where further compression is applied in that domain. The final residual which represents error resulting from the compression and decompression process, is then used as a cost to be minimized by adjusting the configuration of each transformation stage. An adaptive algorithm from earlier works is adopted to iteratively adjust the configuration of each compression stage (selection of coefficients from each transform) to minimize the error. A hierarchical realization of the iterative adaptive algorithm is presented that uses preset compression ratios and optimizes the coefficient selection accordingly. We show that using DCT followed by Haar in the proposed method, it is possible to efficiently compress vehicle trajectory data. The results show that a higher quality for reconstructed data can be achieved using this method, compared to using a single transform compression. For trajectories with sudden movements, the method has a more notable improvement.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 13.56MHz Wireless Power Transfer System with Dual-Output Regulated Active Rectifier for Implantable Medical Devices","authors":"Fu-Bin Yang, J. Fuh, Po-Hung Chen","doi":"10.1109/MWSCAS.2018.8624004","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624004","url":null,"abstract":"In this paper, a 13.56 MHz wireless power transfer system with dual-output regulated active rectifier is developed for implantable medical devices. The rectifier employs pulse-skip modulation (PSM) to regulate two output voltages without using power consuming low dropout regulators (LDOs). The proposed automatic digital offset compensation adjusts both turn-on timing and turn-off timing to compensate the turn-on and turn-off delays of the comparator. The simulation results show that the proposed active rectifier achieves 94% efficiency. The entire wireless power transmission system including power amplifier, resonant tanks, and rectifier, has 67.2% maximum power conversion efficiency (PCE). Compared to the conventional approach with ideal LDOs, 19.2% efficiency improvement is obtained.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131963448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes","authors":"S. Yanagawa, Ryota Shimizu, M. Hamada, T. Kuroda","doi":"10.1109/MWSCAS.2018.8623964","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623964","url":null,"abstract":"This paper proposes a wireless power transfer system which switches between a single frequency mode and a dual frequency mode for 3-D stacked multiple receivers. The power transfer function is analytically formulated in each mode and an optimization methodology of tuning capacitor values is proposed in both modes. An operation scenario switching between two modes is presented and compared with the non-switching mode in terms of the power transfer efficiency. The average power transfer efficiency in the proposed mode is 9.5% higher than the conventional mode.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}