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2016 IEEE East-West Design & Test Symposium (EWDTS)最新文献

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Securing test infrastructure of system-on-chips 保护片上系统的测试基础设施
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807696
Grigor Tshagharyan, Gurgen Harutunyan, S. Shoukourian, Y. Zorian
{"title":"Securing test infrastructure of system-on-chips","authors":"Grigor Tshagharyan, Gurgen Harutunyan, S. Shoukourian, Y. Zorian","doi":"10.1109/EWDTS.2016.7807696","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807696","url":null,"abstract":"The rapid development in the modern technology and its widespread utilization in number of applications brings in new challenges that need to be addressed. Security is one of such challenges that has grown into a major concern over the years. Periodically new incidents of data and system breaches are reported. For this purpose, usually different side channels in the system are being exploited by the attackers to bypass the protection mechanisms. Especially vulnerable with this regard is the traditional test and debug infrastructure placed on the System on Chips (SoC) which provides an alternative path into the chip internal structure. The aim of this paper is to present a comprehensive overview of various security aspects of SoCs including the known threat models, classification of attackers and existing techniques as well as present the solution concept for secure SoC Test Infrastructure with the focus on embedded cores testing.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133658642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A comparative analysis of mutation testing tools for Java Java突变测试工具的比较分析
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807636
Forostyanova Mariya, Dongak Barkhas
{"title":"A comparative analysis of mutation testing tools for Java","authors":"Forostyanova Mariya, Dongak Barkhas","doi":"10.1109/EWDTS.2016.7807636","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807636","url":null,"abstract":"The paper is devoted to the mutation testing technique that is widely used when testing different software tools. This paper presents a comparative analysis of two mutation testing tools for Java programs, namely Pitest and /Java. They both allow automatically introducing faults into a software code. The analysis has revealed their pros and cons, as well as specific features of their launch and application. Such comparison can help to select the choose the most appropriate mutation tool or the combination of these tools when testing Java programs. We further discuss how these two tools might be combined and which of the two tools better for the mutation generation.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131544611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
System on chip for comparison of precise time sources 片上系统用于精确时间源的比较
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807683
J. Dostál, V. Smotlacha
{"title":"System on chip for comparison of precise time sources","authors":"J. Dostál, V. Smotlacha","doi":"10.1109/EWDTS.2016.7807683","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807683","url":null,"abstract":"This paper deals with a precise time, particularly comparison of diverse precise time transfer methods and sources. We deal with two ways of the precise time acquisition - the dedicated time and frequency transfer infrastructure and the time network protocols. For the needs of distinct time and frequency methods evaluation, we designed a FPGA based System on Chip (SoC) that may acquire time and frequency from dedicated time transfer infrastructure or from a standard TCPIP network utilizing IEEE 1588 or NTP protocol. The SoC is implemented on a Zynq field-programmable gate array (FPGA). We also present an experience with the design and intended applications of our system.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122546527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Verification of sampling theorem validity and features for specific cases of transformed samples number 对变换样本数的具体情况下抽样定理的有效性和特征的验证
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807697
G. S. Khanyan
{"title":"Verification of sampling theorem validity and features for specific cases of transformed samples number","authors":"G. S. Khanyan","doi":"10.1109/EWDTS.2016.7807697","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807697","url":null,"abstract":"This paper continues the author's research in the field of sampling theorem for a finite duration signal in a limited frequency band. Verification of the general method of signal conversion for a few individual samples number cases is carried out with maximum completeness, and further direction of the theory development is established.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116853230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
UVM based approaches to functional verification of communication controllers of microprocessor systems 基于UVM的微处理器系统通信控制器功能验证方法
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807695
I. Stotland, D. Shpagilev, N. Starikovskaya
{"title":"UVM based approaches to functional verification of communication controllers of microprocessor systems","authors":"I. Stotland, D. Shpagilev, N. Starikovskaya","doi":"10.1109/EWDTS.2016.7807695","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807695","url":null,"abstract":"The approach to functional verification of communication controllers based on developing layered UVM test systems is considered in this paper. Some benefits of application standalone simulation based verification are marked out. The architecture most of communication controllers could be divided into three logical layers: the transport layer, the channel layer and the physical layer. The main features and functions of the communication controller's layers are described. We proposed the approach which lies in developing one UVM test system and one design under test (DUT) consisting of controllers of each layer. Some novel techniques for checking the correctness of communication controller implementation at all layers are proposed and used. The architecture of the UVM-based test system and functions of its components are presented.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117138606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrodynamic characteristics estimation for aperiodic random composite media 非周期随机复合介质的电动力学特性估计
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807729
D. Bezuglov, M. Zvezdina, L. Cherckesova, Yulia A. Shokova, N. Prokopenko, G. N. Shalamov, G. Sinyavsky, O. Manaenkova
{"title":"Electrodynamic characteristics estimation for aperiodic random composite media","authors":"D. Bezuglov, M. Zvezdina, L. Cherckesova, Yulia A. Shokova, N. Prokopenko, G. N. Shalamov, G. Sinyavsky, O. Manaenkova","doi":"10.1109/EWDTS.2016.7807729","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807729","url":null,"abstract":"The paper presents approaches to electro-dynamic characteristics estimation for artificial composite media, among which a periodic random media are especially distinguished. Resonant circuit implementation based on thin-film ferromagnetic nanostructures is possible in a periodic composite media. Chiral media, photonic, magnonic crystals and layered structures are of particular interest. Approaches based on spin waves excitation are important for ferromagnetic nanostructure study. Propagation and scattering of electromagnetic waves in near-field and far-field regions of plane structure for layered structures in composite media can be described with Maxwell's equations in mag-netostatic approximation, electrodynamic and exchange boundary conditions, and Green's method of tensor functions.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114590903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit 基于故障安全电路的软错误容错顺序电路设计
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807676
S. Ostanin, A. Matrosova, N. Butorina, V. Lavrov
{"title":"A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit","authors":"S. Ostanin, A. Matrosova, N. Butorina, V. Lavrov","doi":"10.1109/EWDTS.2016.7807676","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807676","url":null,"abstract":"This paper presents a fault-tolerant synchronous sequential circuit design based on fault-secure system with low overhead. The scheme has only one fault-secure sequential circuit, a normal (unprotected) sequential circuit, a checker and rather simple XOR circuit. It is proved the reliability properties of the suggested scheme not only for single stuck-at faults at gate poles but for path delay faults transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114597557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Weighted sum code without carries — Is an optimum code with detection of any double errors in data vectors 不带进位的加权和代码-是一种检测数据向量中任何双重错误的最佳代码
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807686
V. Sapozhnikov, D. Efanov, V. Sapozhnikov, V. Dmitriev
{"title":"Weighted sum code without carries — Is an optimum code with detection of any double errors in data vectors","authors":"V. Sapozhnikov, D. Efanov, V. Sapozhnikov, V. Dmitriev","doi":"10.1109/EWDTS.2016.7807686","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807686","url":null,"abstract":"The article provides a method of building the sum code, that detects any errors of double multiplicity in data vectors. This characteristic can be effectively used for organizing the concurrent error detection (CED) systems of combinational logic circuits. The paper explains new sum code characteristics, and also states the properties of this code for error detection in data vectors. Also there is a comparison of a new sum code with the classic Hamming code, also having this characteristic to detect any double errors. Theoretical results are complemented with experimental studies with the system of check combinational circuits MCNC Benchmarks.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
QuaSim — Cloud service for digital circuits simulation 用于数字电路仿真的云服务
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807667
I. Hahanov, Igor Iemelianov, W. Gharibi, Tamer Bani Amer
{"title":"QuaSim — Cloud service for digital circuits simulation","authors":"I. Hahanov, Igor Iemelianov, W. Gharibi, Tamer Bani Amer","doi":"10.1109/EWDTS.2016.7807667","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807667","url":null,"abstract":"A cloud service QuaSim designed for simulation and verification of digital systems based on transactions between the addressable memory components to implement any functionality is proposed. A new approach to the synthesis and analysis of digital systems using vector form (quantum) for defining combinational and sequential structures to implement them in the memory elements is described; it is substantially different from the classical design theory of discrete devices based on the truth tables of the components. Quantum or qubit data structures are used [1-5] for the implementation of computational processes in order to improve the performance of digital systems analysis and reduce memory volume through unary coding the states of input, internal and output variables, and also the implementation of qubit vectors in the FPGA memory elements, which realize combinational and sequential primitives. Implementation of quantum memory-based-only models for describing digital components in the practice of designing computer systems directly affects the increase in product yield, allows improving the reliability of computer products, reducing the cost of designing and manufacturing, and providing standalone human-free remote & online repair.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125411066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of ferromagnetic materials with properties set on nanolevel at resonant circuits creating of microwave (SHF) and THz (EHF) ranges 具有纳米级特性的铁磁材料在微波和太赫兹谐振电路中的应用
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807711
D. Bezuglov, M. Zvezdina, L. Cherckesova, Yulia A. Shokova, N. Prokopenko, G. N. Shalamov, G. Sinyavsky, O. Manaenkova
{"title":"Application of ferromagnetic materials with properties set on nanolevel at resonant circuits creating of microwave (SHF) and THz (EHF) ranges","authors":"D. Bezuglov, M. Zvezdina, L. Cherckesova, Yulia A. Shokova, N. Prokopenko, G. N. Shalamov, G. Sinyavsky, O. Manaenkova","doi":"10.1109/EWDTS.2016.7807711","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807711","url":null,"abstract":"In this paper the available ferromagnetic materials, both the ones that are still under investigation and the ones that are applied in radioelectronics, including nanomagnetics, were analyzed. This analysis allows us to give an estimation of global trends in evolution of ferromagnetic usage in the new generation of SHF (microwave) and EHF devices. The paper accentuates the thin-film ferromagnetic media where the properties are set on nanolevel. These properties enable us to manage ferrostructures parameters and to apply the structures to resonant circuits for nonlinear parametric zonal systems (NPS), which are operating within current ultraharmonics in higher instability zones of electromagnetic oscillations. It is concluded that intense interest for the problem of realization of resonant structures based on NPS, operating on current ultraharmonics in higher instability zones of electromagnetic oscillations in SHF and EHF bands, lies within nanomaterials with several order parameters, especially multiferroics and carbon nanotubes.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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