A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit

Abstract

This paper presents a fault-tolerant synchronous sequential circuit design based on fault-secure system with low overhead. The scheme has only one fault-secure sequential circuit, a normal (unprotected) sequential circuit, a checker and rather simple XOR circuit. It is proved the reliability properties of the suggested scheme not only for single stuck-at faults at gate poles but for path delay faults transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared.