{"title":"MvEcho - acoustic response modelling for auralisation","authors":"Léonie Buckley, Sam Caulfield, D. Moloney","doi":"10.1109/HOTCHIPS.2016.7936238","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936238","url":null,"abstract":"•Auralisation is the process of simulating the listening experience at a given position. •While many auralisation algorithms currently exist, the majority require a manual description of the environment. •In contrast, MvEcho removes the need for this manual description to provide an environment independent algorithm to approximate auralisation. •Initial implementation of MvEcho concerned the acoustic response of objects, namely the pyramid El Castillo, (shown below in Fig. 1) and has now been extended to model the response of rooms. •The algorithm is fully functional in C and is currently being ported to the Myriad 2.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127330388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, S. Srinath, T. Pritchard, Robin Ying, C. Batten
{"title":"Experiences using a novel Python-based hardware modeling framework for computer architecture test chips","authors":"Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, S. Srinath, T. Pritchard, Robin Ying, C. Batten","doi":"10.1109/HOTCHIPS.2016.7936233","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936233","url":null,"abstract":"This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122099171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"QORIQ® LS1012A: Big things in small packages: 64-bit core in a sub-10mm package","authors":"Ben Eckermann","doi":"10.1109/HOTCHIPS.2016.7936227","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936227","url":null,"abstract":"This article consists only of a collection of slides from the author's conference presentation.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inuitive breakthrough solution for AR and VR worlds","authors":"Dor Zepeniuk","doi":"10.1109/HOTCHIPS.2016.7936197","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936197","url":null,"abstract":"","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122315504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pascal GPU with NVLink","authors":"John Danskin, D. Foley","doi":"10.1109/HOTCHIPS.2016.7936202","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936202","url":null,"abstract":"This article consists only of a collection of slides from the author's conference presentation.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3D sensors for the rest of us","authors":"Larry Yang","doi":"10.1109/HOTCHIPS.2016.7936194","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936194","url":null,"abstract":"This article consists only of a collection of slide images from the author's conference presentation.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded deep neural networks: “The cost of everything and the value of nothing”","authors":"D. Moloney","doi":"10.1109/HOTCHIPS.2016.7936219","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936219","url":null,"abstract":"•Deep Learning for Embedded is all about Inference •Standard Networks are designed to achieve high-accuracy •Embedded implementation on architectures such as Movidius VPU can achieve significant performance results at the network edge •Next challenge is to further optimise networks to maximise performance per Watt","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126528285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Software in Silicon in the Oracle SPARC M7 processor","authors":"K. Aingaran, Sumti Jairath, D. Lutz","doi":"10.1109/HOTCHIPS.2016.7936220","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936220","url":null,"abstract":"1 SW in Silicon is custom hardware targeted at specific higher level functions traditionally implemented in software 2 Cloud based applications, especially analytics, offer many opportunities for SW in Silicon features 3 SW in Silicon in SPARC M7 provides gains in Performance, Power, Security and Memory Capacity 4 Oracle database automatically uses these SW in Silicon features. Other applications access through public API 5 Oracle is researching tighter HW-SW codesign, targeting deeper gains on a wider set of applications","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123478302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The bifrost GPU architecture and the ARM Mali-G71 GPU","authors":"J. Davies","doi":"10.1109/HOTCHIPS.2016.7936201","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936201","url":null,"abstract":"■ Leverages Mali's scalable architecture ■ Scalable to 32 shader cores ■ Major shader core redesign ■ New scalar, clause-based ISA ■ New quad-based arithmetic units ■ New geometry data flow ■ Reduces memory bandwidth and footprint ■ Support for fine grain buffer sharing with the CPU","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}