{"title":"LiveSynth: Towards an interactive synthesis flow","authors":"R. T. Possignolo, Jose Renau","doi":"10.1145/3061639.3062275","DOIUrl":"https://doi.org/10.1145/3061639.3062275","url":null,"abstract":"➔ The incremental step of LiveSynth reduces synthesis time by about 95% for incremental changes. ➔ LiveSynth shifts the paradigm to small, incremental changes and more iterations per day. ➔ We advocate for an interactive synthesis flow as a way to boost design productivity.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125697927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HW acceleration for volumetric applications","authors":"D. Moloney","doi":"10.1109/HOTCHIPS.2016.7936196","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936196","url":null,"abstract":"•Volumetric applications can run efficiently on embedded platforms •Optimal data-structures can allow 128× reduction in RAM requirements •Bit-per-voxel Octree allows compact interchangeable format for M2M •Two bit's per voxel allows colour and other information to be stored per sub-volume","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114677706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ARMv8-A next-generation vector architecture for HPC","authors":"Nigel Stephens","doi":"10.1109/HOTCHIPS.2016.7936203","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936203","url":null,"abstract":"This article consists only of a collection of slides from the author's conference presentation.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124165049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HBM package integration: Technology trends, challenges and applications","authors":"S. Ramalingam","doi":"10.1109/HOTCHIPS.2016.7936172","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936172","url":null,"abstract":"❯ Tb/s low latency bandwidth and lower system power is driving the need for HBM adoption ❯ Silicon Interposer (2.5D) is the incumbent technology of choice. Potentially lower cost, fine pitch interconnect wafer-level and substrate based technologies are emerging ❯ To drive broader adoption of HBM applications (cooling limited) and higher performance stacks (8-Hi), higher HBM junction temperature (>95C) needs to be supported","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reconfigure your RTL with EFLX join the SoC revolution","authors":"C. C. Wang, D. Markovic","doi":"10.1109/HOTCHIPS.2016.7936234","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936234","url":null,"abstract":"","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124342203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Efland, Sandip Parikh, H. Sanghavi, A. Farooqui
{"title":"High performance DSP for vision, imaging and neural networks","authors":"G. Efland, Sandip Parikh, H. Sanghavi, A. Farooqui","doi":"10.1109/HOTCHIPS.2016.7936210","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936210","url":null,"abstract":"","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and development of a an ultra-low power Intel architecture MCU class SoCs","authors":"Peter Barry","doi":"10.1109/HOTCHIPS.2016.7936206","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936206","url":null,"abstract":"■ First iteration right ballpark in terms of performance/area/power/cost ■We Continue to -Continue to iterate on the micro architecture -Process related micro-architecture evolution -Analog IP evolution","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122910320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, M. Lattuada, Fabrizio Ferrandi
{"title":"A dynamically scheduled architecture for the synthesis of graph methods","authors":"Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, M. Lattuada, Fabrizio Ferrandi","doi":"10.1109/HOTCHIPS.2016.7936228","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2016.7936228","url":null,"abstract":"","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}