{"title":"Scheduling strategies for multitasking in a distributed system","authors":"H. Karatza","doi":"10.1109/SIMSYM.2000.844904","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844904","url":null,"abstract":"We study various policies for scheduling tasks in distributed processor queues. Their performance is studied and compared for a variety of workloads. It is our intention to find a policy that increases throughput and also is fair to jobs. Simulation results indicate that the policy that schedules the shortest task in a queue, when there is not any other task that has been waiting more than some configurable period of time, yields good system performance and also provides a guarantee for fairness in individual job execution.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132803145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance analysis of multiprocessor architectures via analytical simulation","authors":"A. Veglis, A. Pomportsis","doi":"10.1109/SIMSYM.2000.844931","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844931","url":null,"abstract":"The performance analysis of network architectures is a very crucial factor in designing multiprocessor systems. Very often, simulation is the only feasible method because of the nature of the problem and because analytical techniques become too difficult to handle. However simulation can be costly to develop and run. The mathematical analysis approach is preferable but in most cases not applicable. This paper presents an analytical simulation method that can be used for the evaluation of interconnection network architectures that are based on buffered banyan networks. This method comprises the probabilistic analysis and the simulation technique, with the help of a mathematical software package MathConnex (of MathSoft Corporation). The analysis enables us to observe the behavior of various stages of the network architecture, under various traffic conditions.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123023110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flow control and dynamic load balancing in Time Warp","authors":"Myongsu Choe, C. Tropper","doi":"10.1109/SIMSYM.2000.844919","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844919","url":null,"abstract":"We present an algorithm which integrates flow control and dynamic load balancing in Time Warp. The algorithm is intended for use in a distributed memory environment. Our flow control algorithm makes use of stochastic learning automata and is similar to the leaky-bucket flow control algorithm used in computer networks. It regulates the flow of messages between processors continously throughout the course of the simulation, while the dynamic load balancing algorithm is invoked only when a load imbalance is detected. We compare the perfomance of the flow control algorithm, the dynamic load balancing algorithm and the integrated algorithm with that of a simulation without these controls. We simulated large shuffle ring networks with and without hot spots and a PCS network on an SGI Origin 2000 system. Our results indicate that the flow control scheme alone succeeds in greatly reducing the number and length of rollbacks as well as the number of anti-messages, thereby increasing the number of non-rolledback messages processed per second. It results in a large reduction in the amount of memory used and outperforms the dynamic load balancing algorithm for these measures. The integrated scheme produces even better results for all of these measures and results in reduced execution times.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124524496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal resource allocation for multi-service networks","authors":"R. Simon, B. Jukic, Woan Sun Chang","doi":"10.1109/SIMSYM.2000.844898","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844898","url":null,"abstract":"The next generation of communication networks will simultaneously offer multiple service classes capable of supporting both real-time and best-effort traffic. At the level of an individual network router or gateway, a critical question that needs to be addressed is the development of a set of policies and metrics to determine how router resources should be shared between different service classes. We describe a solution to this problem that combines pricing policies with admission control for real-time traffic. We present a measurement-based approach for adaptive pricing that results in near-optimal resource allocation policies between real-time and best-effort traffic. We also show, through simulation, an application of our approach that maximizes overall user value.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation-trace-based component performance prediction","authors":"J. J. Li, J. R. Horgan","doi":"10.1109/SIMSYM.2000.844926","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844926","url":null,"abstract":"Large software systems are composed of interdependent distributed components, some developed in-house, some commercially available, and others developed by the customer. The system architecture, that is, the components comprising the system and their interconnections, typically varies for each design. Performance prediction is important for such software, including helping designers to select better designs and helping them to adjust the software architecture for better performance. To predict the overall system performance, we must have performance data for each component. Performance modelling for reused components was reported elsewhere. This paper presents a technology and its accompanying tool suite to obtain performance models of new components in a formal software architectural design specification given in a communicating extended finite state machine (CEFSM) model. Performance data for such new components are not available and must be collected through simulation. Our technique includes three steps: component specification instrumentation; simulation; and component stochastic performance model derivation from simulation trace. We applied our technology to a telecom application to predict the performance of its new components. Combined with the performance models of reused components from previous work, we were able to predict performance of the entire architectural design.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128132430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MICA: a memory and interconnect simulation environment for cache-based architectures","authors":"Hung-Chang Hsiao, C. King","doi":"10.1109/SIMSYM.2000.844930","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844930","url":null,"abstract":"MICA is a new-generation simulation environment, which provides complete simulation facilities for simulating distributed shared memory (DSM) multiprocessors. It runs on the inexpensive Linux-based PCs. MICA uses application traces as inputs and provides a core scheduler and memory, and interconnect interfaces. A rich set of synchronization algorithms and architecture simulator are also provided. We introduce the MICA simulator environment and demonstrate its use in investigating the effectiveness of one-to-many (multicast) communication for write invalidation in DSM multiprocessors.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128230029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Handling behavioral components in multi-level concurrent fault simulation","authors":"K. Panetta, Jonathan B. Homer","doi":"10.1109/SIMSYM.2000.844911","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844911","url":null,"abstract":"System level modeling is becoming a necessity in all areas of engineering design. As systems grow in complexity, designers may increasingly rely on commercial off-the-shelf (COTS) components. Frequently, these components are described at a high level of abstraction (behaviorally) that complicates fault testing. We discuss the trade-offs of using behavioral components in a design, specifically as it relates to fault simulation. We investigate important issues such as timing, and examine the need to internally-fault behavioral models. We then present our fault-level concurrent fault simulator (MCS) that can accept any combination of gate level and behavioral models using a single kernel. Our kernel propagates faults through behavioral components deterministically. Finally, we present performance results of multi-level models to demonstrate the simulator's capabilities and performance.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"50 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120920591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling and simulation of a fault tolerant ATM switching architecture","authors":"M. Anan, M. Guizani","doi":"10.1109/SIMSYM.2000.844899","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844899","url":null,"abstract":"Multistage interconnection networks (MINs) have been proposed as the switching fabrics for B-ISDN. With the throughput requirement of the packet switches exceeding several gigabits/sec, it becomes important to make them fault tolerant. To provide fault tolerance and improve network performance, a new fault-tolerant, self-routing, and high performance switching architecture for ATM networks based on MINs is proposed. It consists of two closely linked Banyan networks. Links are provided at every stage to allow cells to transfer to and from each plane. The performance and the reliability of the proposed architecture is compared to the other networks. The proposed network has low cell loss rate probabilities than other networks for both fault-free and faulty environments. Routing is kept simple as in basic MINs. Furthermore, the proposed switch architecture is modular in its design making it ideal for VLSI implementation.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129751593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrating discrete and continuous phenomena models into practical advanced user interface specifications","authors":"S. A. Morrison","doi":"10.1109/SIMSYM.2000.844929","DOIUrl":"https://doi.org/10.1109/SIMSYM.2000.844929","url":null,"abstract":"Most current user interface specification languages and toolkits are based on serial, discrete, token exchange paradigms that perform an acceptable job of implementing traditional WIMP (Window, Icon, Menu, Pointer) interfaces. These tools, however are ill suited to address the needs of emerging interaction studies such as virtual environments and interactive simulations. These interaction styles commonly rely upon full duplex, asynchronous, interrelated dialogues, a blend of continuous and discrete inputs and responses, and implicit commands and probabilistic input events. Some forms of non-WIMP interfaces, particularly interactive simulations, must also contend with real time processing constraints and deadline-based computations. This work proposes a specification paradigm, the SHADOW system, which directly addresses these issues. This system has been demonstrated to allow both the semantic meaning and behavior of all simulation elements to be clearly defined in a reusable fashion while providing support for good software engineering practices.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126983577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}