{"title":"MICA: a memory and interconnect simulation environment for cache-based architectures","authors":"Hung-Chang Hsiao, C. King","doi":"10.1109/SIMSYM.2000.844930","DOIUrl":null,"url":null,"abstract":"MICA is a new-generation simulation environment, which provides complete simulation facilities for simulating distributed shared memory (DSM) multiprocessors. It runs on the inexpensive Linux-based PCs. MICA uses application traces as inputs and provides a core scheduler and memory, and interconnect interfaces. A rich set of synchronization algorithms and architecture simulator are also provided. We introduce the MICA simulator environment and demonstrate its use in investigating the effectiveness of one-to-many (multicast) communication for write invalidation in DSM multiprocessors.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIMSYM.2000.844930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
MICA is a new-generation simulation environment, which provides complete simulation facilities for simulating distributed shared memory (DSM) multiprocessors. It runs on the inexpensive Linux-based PCs. MICA uses application traces as inputs and provides a core scheduler and memory, and interconnect interfaces. A rich set of synchronization algorithms and architecture simulator are also provided. We introduce the MICA simulator environment and demonstrate its use in investigating the effectiveness of one-to-many (multicast) communication for write invalidation in DSM multiprocessors.