Modeling and simulation of a fault tolerant ATM switching architecture

Abstract

Multistage interconnection networks (MINs) have been proposed as the switching fabrics for B-ISDN. With the throughput requirement of the packet switches exceeding several gigabits/sec, it becomes important to make them fault tolerant. To provide fault tolerance and improve network performance, a new fault-tolerant, self-routing, and high performance switching architecture for ATM networks based on MINs is proposed. It consists of two closely linked Banyan networks. Links are provided at every stage to allow cells to transfer to and from each plane. The performance and the reliability of the proposed architecture is compared to the other networks. The proposed network has low cell loss rate probabilities than other networks for both fault-free and faulty environments. Routing is kept simple as in basic MINs. Furthermore, the proposed switch architecture is modular in its design making it ideal for VLSI implementation.