2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)最新文献_第10页

High-resolution Time-domain Reflectometry Analysis in Back-end-of-line (BEOL) by Recursive Circuit Modelling 基于递归电路模型的高分辨率时域反射分析

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654424

Y. Shang, M. Shinohara, Rahul Babu Radhamony, J. Kiljan, Alan Wu

引用次数: 1

Modeling and Control of Hybrid Si-Based Micro-Fluid Cooling System for Data Center Application 数据中心混合硅基微流体冷却系统的建模与控制

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654447

Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang

{"title":"Modeling and Control of Hybrid Si-Based Micro-Fluid Cooling System for Data Center Application","authors":"Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654447","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654447","url":null,"abstract":"Liquid cooling system for IT device shows potential of energy efficiency, which is very attractive to data center owner. To exploit the capability of the liquid cooling system, proper controller should be designed. This paper presents the design of model and controller for the liquid cooling system. First, the mathematical models for each individual component are derived from physical laws. Model parameters are determined by the performance curve. Based on the working point selection program and control parameter optimization process, the proportional-integration controller with feedforward path (PI-FF) is designed. Target tracking task and disturbance rejection task are used to evaluate the performance of the PI-FF controller. The results and simulations not only validate the capability of proposed control method, but also in-depth revealed the key physical bottleneck that prevent improving the response of the controller. This result suggests that heat transfer process from junction to the coolant should be as shot as possible, and therefore direct bonding the micro cooler to the chip could be the most efficient way to reduce their interface thickness.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

RDL Process Development of MEMS Wafer Level Chip Scale Packaging with Silicon Pillar/CuPd as Through Mold Interconnection 以硅柱/CuPd为通模互连的MEMS晶圆级芯片级封装RDL工艺开发

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654373

Lau Boon Long, C. Zhaohui, Simon Lim Siak Boon, Sharon Lim Pei Siang

{"title":"RDL Process Development of MEMS Wafer Level Chip Scale Packaging with Silicon Pillar/CuPd as Through Mold Interconnection","authors":"Lau Boon Long, C. Zhaohui, Simon Lim Siak Boon, Sharon Lim Pei Siang","doi":"10.1109/EPTC.2018.8654373","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654373","url":null,"abstract":"This paper is presenting the fabrication of wafer substrate level chip-scale packaging process on MEMS. The key processes are to develop the over-mold wafer level chip-scale packaging solution for MEMS which using metal deposited silicon pillar and Cu/Pd vertical wire as through-mold interconnection (TMI). Wafer level RDL process to route the contact point to UBM bumping pads which going to bond with PCB. The key challenges and process steps are discussed here: Wafer level epoxy molding materials selection; several approaches on molding process optimization; silicon to epoxy molded layers density and thickness ratio control and post mold curing conditions settings were studied to minimize the wafer warpage at <1.5 mm which was induced from CTE mismatch between silicon and epoxy materials. After backgrinding process to reveal the silicon pillar or Cu/Pd vertical wire contact surfaces; subsequent RDL processes are following by physical vapour deposition (PVD) to deposit metal seed layer, electroplating process (ECP) to build the copper metal lines on selective area which isolated by photoresist patterning; spin-coating process with photosensitive materials to build dielectric layers and developed contact/via opening. Process parameters are optimized to control the thermal budget accumulated from each process steps to minimize the wafer warpage within process window. Dielectric and epoxy mold material evaluation results is presented. The electrically test and reliability test was measured to examine the RDL process connection results and reliability.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115653338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fine Pitch Solder Paste (T7) for System in Package (SiP) Applications 用于系统级封装(SiP)应用的细间距锡膏(T7)

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654414

Zhang Ruifen, Chiong, Kung Chuan Kenny, V. Sureshkumar, Chan Li-san

{"title":"Fine Pitch Solder Paste (T7) for System in Package (SiP) Applications","authors":"Zhang Ruifen, Chiong, Kung Chuan Kenny, V. Sureshkumar, Chan Li-san","doi":"10.1109/EPTC.2018.8654414","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654414","url":null,"abstract":"System in Package (SIP) is a high level integration of different components, dies and chips in one package to achieve multiple function in one system. Solder paste, as a common assembly material, plays the role to connect the components, dies and chips to the substrate to form one package. The dimension of components, die and chip have a big variation in one package, it needs a few different application process to complete the entire package assembly. A new water soluble solder paste (T7 powder) with good printing performance was developed, it can be applied in SiP through printing process to achieve the passive component attach, die attach and flip chip all in one process. The printing performance of a solder paste is critical to improve the production yield in System in Package (SiP). This research work studied the impact of powder type –Type 5, Type 6, Type 7 on the paste printing performance in fine pitch application, mainly on the paste volume deposition and consistency with small opening. The highlight of this paper is to present the excellent printing performance of the newly developed water soluble paste (T7 powder), which can print down to 50um stencil opening with consistent volume deposition and no bridging with line space down to 40um. The void, tombstone and solder bead performance were also tested with 01005 components under actual component attach simulation. The existence of void in solder joint would affect the thermal conductivity and electrical conductivity of the device and hence, minimizing the void in solder joint is critical to improve the reliability of the whole package. This research work also studied on how to reduce void by adjusting reflow profile and applying vacuum during reflow, especially with flip chip and bigger die sizes.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The Balun Design by Embedding High Permittivity Material in The Substrate of CSP Package with Large Size 大尺寸CSP封装衬底嵌入高介电常数材料的Balun设计

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654314

Y. Lu, Bo-Siang Fang, Hsuan-Hao Mi, Kuan-Ta Chen, Mike Tsai

引用次数: 0

Simulation And Electrical Characterization Of A Novel 2D-Printed Incontinence Sensor With Conductive Polymer PEDOT:PSS For Medical Applications 一种新型2d打印失禁传感器的模拟和电气特性与导电聚合物PEDOT:PSS医疗应用

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654420

Manuel Baeuscher, Bei Wang, Xiaodong Hu, P. Mackowiak, Norman Merchau, O. Ehrmann, M. Schneider-Ramelow, K. Lang, H. Ngo

{"title":"Simulation And Electrical Characterization Of A Novel 2D-Printed Incontinence Sensor With Conductive Polymer PEDOT:PSS For Medical Applications","authors":"Manuel Baeuscher, Bei Wang, Xiaodong Hu, P. Mackowiak, Norman Merchau, O. Ehrmann, M. Schneider-Ramelow, K. Lang, H. Ngo","doi":"10.1109/EPTC.2018.8654420","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654420","url":null,"abstract":"Due to the growing numbers of elderly people in the world, who suffer from incontinence and are in the need of care, technologies are necessary to increase the effectiveness of nursing staff and enhance the hygiene for humans to improve life quality. For this reason a low cost humidity sensor system printed onto the substrate of a diaper with the novel organic conductive ink PEDOT:PSS (Poly (3,4-ethylenedioxythio-phene):Poly(styrene sulfonate)) was developed in previous work [1]. The novel material PEDOT:PSS is still expensive because of rare use in research and market demand. Therefore a way for optimization of the sensor is aimed to print the sensor with less material, but at the same time with no loss of sensitivity. With this purpose, two theoretical models are developed. An analytic model with geometrical based calculations and a Finite Element Analysis (FEA) simulation model, for deeper understanding of electric field effects with focus on the total capacitance of the sensor. To verify these theoretical models a characterization measurement of manufactured samples of previous work [1] is made, to obtain a comparison between every experimental method. For the theoretical models the necessary material parameters are characterized.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"87 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124997535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Millimeter wave resonator and cavity-back slot antenna in Fan-Out Wafer Level Packaging 扇出晶圆级封装中的毫米波谐振器和后腔槽天线

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654410

C. Zihao, Lim Teck Guan

引用次数: 1

Combined Thick Resist Processing and Topography Patterning for Advanced Metal Plating 高级金属镀层的复合厚抗蚀剂加工和形貌图像化

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654312

M. Eibelhuber, J. Rimböck, T. Zenger, T. Uhrmann, T. Matthias

引用次数: 1

Constitutive Behaviour of Single Lap Joint of Sintered Silver Paste 烧结银浆单搭接本构特性研究

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654407

X. Long, C. Du, Wenbin Tang, Yongchao Liu, Yao Yao, Fengrui Jia

引用次数: 0

Modeling and simulation of chemical amplification photoresist to produce high-density cone-shaped micro bumps 化学放大光刻胶产生高密度锥形微凸点的建模与仿真

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) Pub Date : 2018-12-01 DOI: 10.1109/EPTC.2018.8654401

Daiki Kumagwa, M. Sakamoto, Yohei Aoki, T. Asano

引用次数: 0