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A Low-Power and High-Quality Cordic Based Loeffler DCT 基于Cordic的低功耗高质量吕弗勒DCT
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258132
Chi-Chia Sun, B. Heyne, S. Ruan, Juergen Goetze
{"title":"A Low-Power and High-Quality Cordic Based Loeffler DCT","authors":"Chi-Chia Sun, B. Heyne, S. Ruan, Juergen Goetze","doi":"10.1109/VDAT.2006.258132","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258132","url":null,"abstract":"In this paper, a low-power and high-quality preserving DCT architecture is presented. It is obtained by optimizing the Loeffler DCT based on the Cordic algorithm. The experimental results show that the proposed DCT architecture occupies 19% of the area and consumes about 16% of the power compared to the original Loeffler DCT. Additionally the good transformation quality is retained. In this regard, the proposed Cordic based Loeffler DCT is very suitable for low-power and high-quality CODECs, especially for battery-based systems","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128928455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Automatic Low Power Optimizations during ADL-driven ASIP Design 在adl驱动的ASIP设计过程中的自动低功耗优化
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258140
A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr
{"title":"Automatic Low Power Optimizations during ADL-driven ASIP Design","authors":"A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr","doi":"10.1109/VDAT.2006.258140","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258140","url":null,"abstract":"Increasing complexity of cutting-edge applications for future embedded systems demand even higher processor performance with a strong consideration for battery-life. Low power optimization techniques are, therefore, widely applied towards the development of modern application specific instruction-set processors (ASIPs). Architecture description languages (ADLs) offer the ASIP designers a quick and optimal design convergence by automatically generating the software tool-suite as well as the register transfer level (RTL) description of the processor. The automatically generated processor description is then subjected to the traditional RTL-based synthesis flow. Power-specific optimizations, often found in RTL-based commercial tools, cannot take the full advantage of the architectural knowledge embedded in the ADL description, resulting in sub-optimal power efficiency. In this paper, we address this issue by describing an efficient and universal technique of automatic insertion of gated clocks during the ADL-based ASIP design flow. Experiments with ASIP benchmarks show the dramatic impact of our approach by reducing power consumption up to 41% percent compared to naive RTL synthesis from ADL description, without any incurred overhead for area and speed","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Adaptive Quadrature Clock Generator 自适应正交时钟发生器
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258160
J. Huang, Chih-Hsien Lin, S. Jou
{"title":"Adaptive Quadrature Clock Generator","authors":"J. Huang, Chih-Hsien Lin, S. Jou","doi":"10.1109/VDAT.2006.258160","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258160","url":null,"abstract":"In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13mum 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Adaptive 3.125Gbps Coaxial Cable Equalizer 自适应3.125Gbps同轴电缆均衡器
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258164
J. Lu, Chi-Lun Luo, Shen-Iuan Liu
{"title":"An Adaptive 3.125Gbps Coaxial Cable Equalizer","authors":"J. Lu, Chi-Lun Luo, Shen-Iuan Liu","doi":"10.1109/VDAT.2006.258164","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258164","url":null,"abstract":"In this paper, an adaptive 3.125Gbps coaxial cable equalizer is realized in a 0.18-mum CMOS technology. For the length of 15m and 20m Belden 8219 cables, the signal attenuation are -12dB and -16dB, respectively, at 1.5625GHz. Due to the signal attenuation after passing through the coaxial cable, this adaptive 3.125Gbps coaxial cable equalizer compensates the broadband loss to be adaptive to different length of the cables. The core circuit excluding output buffers dissipates only 14.8mW from a 1.8V supply with output swing up to 400mV p-p. The core circuit occupies 0.5times0.63mm2 and the measured timing jitter for a cable of 20m is less than 0.25UI","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"37 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121693483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs 一种基于分区的双电源电压标度算法用于低功耗设计
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258141
Hung Hsie Lee, S. H. Tsai, J. Chi, Mely Chen Chi
{"title":"A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs","authors":"Hung Hsie Lee, S. H. Tsai, J. Chi, Mely Chen Chi","doi":"10.1109/VDAT.2006.258141","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258141","url":null,"abstract":"We proposed an effective voltage scaling technique to assign the supply voltage to gates in the circuit of dual power supplies. The algorithm is composed of a greedy voltage assignment phase and an iterative voltage re-assignment refinement phase. It reduces the total power without performance degradation. We apply the algorithm to several test cases. It shows that on average the total power saved is 54.7%. Compared to the GECVS technique (Kulkami, 2004), our algorithm reduces the number of level converters by 23.2% and the power consumption by 5.5%. The experimental result also shows the distribution of slack in the original and the power optimized designs. It shows that majority slacks of the gates are reduced. The algorithm utilizes the slack of gates to scale down the supply voltage of the gates such that the power consumption is reduced","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design Trade-offs for Low-power and High Figure-of-merit LNA 低功耗和高品质因数LNA的设计权衡
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258117
Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu
{"title":"Design Trade-offs for Low-power and High Figure-of-merit LNA","authors":"Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu","doi":"10.1109/VDAT.2006.258117","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258117","url":null,"abstract":"We report a 5.4 mW ultra low dc power low noise amplifier (LNA) at 5.5 GHz, which is based on a 0.35-mum BiCMOS technology. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the usage of the HBT-cascade-MOS methodology is simultaneously satisfied the tradeoff between noise figure (NF) and linearity of LNA. This amplifier achieves a gain/(NF times PDC ) ratio figure of merit of 0.774 (1/mW) which is the better reported at 5~6-GHz band and suitable for wireless LAN applications","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization 从外围专用集成电路设计到区域io倒装芯片设计的芯片I/O规划与合法化
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258146
Chia-Yi Chang, Hung-Ming Chen
{"title":"Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization","authors":"Chia-Yi Chang, Hung-Ming Chen","doi":"10.1109/VDAT.2006.258146","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258146","url":null,"abstract":"Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains 扫描链保持时间故障诊断的鲁棒新范式
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1049/iet-cdt:20060205
Chao-Wen Tzeng, Jeffrey Hsu, Shi-Yu Huang
{"title":"A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains","authors":"Chao-Wen Tzeng, Jeffrey Hsu, Shi-Yu Huang","doi":"10.1049/iet-cdt:20060205","DOIUrl":"https://doi.org/10.1049/iet-cdt:20060205","url":null,"abstract":"Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm are proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133340108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 2.4-GHz/3.5-GHz/5-GHz multi-band LNA with complementary switched capacitor multi-tap inductor in 0.18μm CMOS 2.4 ghz /3.5 ghz /5 ghz多频段LNA，互补开关电容多抽头电感，0.18μm CMOS
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258129
Wei-Chang Li, Chao-Shiun Wang, Chorng-Kuang Wang
{"title":"A 2.4-GHz/3.5-GHz/5-GHz multi-band LNA with complementary switched capacitor multi-tap inductor in 0.18μm CMOS","authors":"Wei-Chang Li, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/VDAT.2006.258129","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258129","url":null,"abstract":"This paper proposes a multi-band low noise amplifier design for WMAN and WLAN applications. The target frequency bands include licensed bands of 2.3 GHz, 2.5 ~ 2.7 GHz and 3.5 ~3.7 GHz, and un-licensed bands of ISM 2.4 GHz and U-NII 5 GHz. The LNA adopts a band selection technique that uses a multi-tap inductor with complementary switch capacitor array. The measured NFs and IIP3s of the proposed LNA are 6.5 dB and -3 dBm at 2.4 GHz, 7.6 dB and -5 dBm at 3.5 GHz, and 8.5 dB and +1 dBm at 5.2 GHz, respectively. The insertion gain S21's are 15 dB at 2.4 GHz, 17 dB at 3.5 GHz, and 15.4 dB at 5.4 GHz. Using a 0.18μm CMOS process, the multi-band LNA dissipates 14.6 mW at 2.4 GHz, and 27.7 mW at 3.5 and 5 GHz without output buffer from a 1.8-V supply voltage","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121055046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Alpha and Neutron SER of embedded-SRAM and Novel Estimation Method 嵌入式sram的Alpha和Neutron SER及其新估计方法
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258118
T. Fukuda, S. Hayakawa, N. Shigyo
{"title":"Alpha and Neutron SER of embedded-SRAM and Novel Estimation Method","authors":"T. Fukuda, S. Hayakawa, N. Shigyo","doi":"10.1109/VDAT.2006.258118","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258118","url":null,"abstract":"Alpha and neutron SERs of embedded-SRAMs are evaluated. From the results for several technology generations, SER is expressed as a function of diffusion area and critical charge for devices, but the effect of collection efficiency is constant for the generations. Then, the technology independent SER model named universal curve is introduced. Moreover, SER trend to 45nm generation is quantitatively estimated based on the future trend of device technology","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114833470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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