2006 International Symposium on VLSI Design, Automation and Test最新文献_第2页

A Low-Power and High-Quality Cordic Based Loeffler DCT 基于Cordic的低功耗高质量吕弗勒DCT

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258132

Chi-Chia Sun, B. Heyne, S. Ruan, Juergen Goetze

引用次数: 12

Automatic Low Power Optimizations during ADL-driven ASIP Design 在adl驱动的ASIP设计过程中的自动低功耗优化

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258140

A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr

{"title":"Automatic Low Power Optimizations during ADL-driven ASIP Design","authors":"A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr","doi":"10.1109/VDAT.2006.258140","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258140","url":null,"abstract":"Increasing complexity of cutting-edge applications for future embedded systems demand even higher processor performance with a strong consideration for battery-life. Low power optimization techniques are, therefore, widely applied towards the development of modern application specific instruction-set processors (ASIPs). Architecture description languages (ADLs) offer the ASIP designers a quick and optimal design convergence by automatically generating the software tool-suite as well as the register transfer level (RTL) description of the processor. The automatically generated processor description is then subjected to the traditional RTL-based synthesis flow. Power-specific optimizations, often found in RTL-based commercial tools, cannot take the full advantage of the architectural knowledge embedded in the ADL description, resulting in sub-optimal power efficiency. In this paper, we address this issue by describing an efficient and universal technique of automatic insertion of gated clocks during the ADL-based ASIP design flow. Experiments with ASIP benchmarks show the dramatic impact of our approach by reducing power consumption up to 41% percent compared to naive RTL synthesis from ADL description, without any incurred overhead for area and speed","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Adaptive Quadrature Clock Generator 自适应正交时钟发生器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258160

J. Huang, Chih-Hsien Lin, S. Jou

引用次数: 1

An Adaptive 3.125Gbps Coaxial Cable Equalizer 自适应3.125Gbps同轴电缆均衡器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258164

J. Lu, Chi-Lun Luo, Shen-Iuan Liu

引用次数: 2

A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs 一种基于分区的双电源电压标度算法用于低功耗设计

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258141

Hung Hsie Lee, S. H. Tsai, J. Chi, Mely Chen Chi

引用次数: 1

Design Trade-offs for Low-power and High Figure-of-merit LNA 低功耗和高品质因数LNA的设计权衡

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258117

Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu

引用次数: 2

Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization 从外围专用集成电路设计到区域io倒装芯片设计的芯片I/O规划与合法化

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258146

Chia-Yi Chang, Hung-Ming Chen

引用次数: 2

Alpha and Neutron SER of embedded-SRAM and Novel Estimation Method 嵌入式sram的Alpha和Neutron SER及其新估计方法

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258118

T. Fukuda, S. Hayakawa, N. Shigyo

引用次数: 3

A Merged LNA-Mixer Design with On-Chip Balun 集成片上Balun的lna混频器设计

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258184

Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu

引用次数: 0

A Power Efficient and Fast Transient Response Low Drop-Out Regulator in Standard CMOS Process 标准CMOS工艺中一种高效、快速的瞬态响应低差稳压器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258163

Chung-Wei Lin, Yen-Jen Liu

{"title":"A Power Efficient and Fast Transient Response Low Drop-Out Regulator in Standard CMOS Process","authors":"Chung-Wei Lin, Yen-Jen Liu","doi":"10.1109/VDAT.2006.258163","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258163","url":null,"abstract":"In this paper a low drop out regulator (LDO) is proposed, which can adaptively change driving current to the PMOS gate and have a fast transient response time. As we know, LDO circuits have to provide a regulated output voltage regardless of input voltage variation, load current variation, and process variation. A load transient test will test the transient behavior of changing output loading. In order to get a good performance in a load transient testing, a buffer with current driving capability is usually added in front of PMOS gate to make the transient response faster. This buffer needs to drive the PMOS gate, and it will consume a few quiescent current in LDO circuits. This static quiescent current will occupy a few percentage of power consumption of LDO circuits at a light load condition, and the efficiency of the LDO at a light load condition will be very poor. In this paper, we proposed a new architecture of LDO, which can adaptively change the driving current of the buffer to the PMOS gate. Then we can improve the efficiency of the LDO up to 10% at light load condition. Meanwhile, we can have a fast transient response time. The load transient response time from 1mA to 138mA is about 2mus, which is faster than other reference designs. This chip is manufactured in 0.35mum standard CMOS process, and it consumes 24muA in a light load condition","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17