{"title":"Research opportunities for nanoscale CMOS","authors":"H. Wong","doi":"10.1109/IWNC.2006.4570976","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570976","url":null,"abstract":"In this paper, the authors analyze the potential performance advantages of using III-V compound semiconductors to provide high device performance. The performance of ultra-thin body double-gate FETs of various III-V compound semiconductors (GaAs, InAs, InSb) was analyzed and compared with Ge and Si. The performance limits of ultra-thin body double-gated (DG) III-V channel MOSFETs are presented in this paper. An analytical ballistic model including all the valleys (Gamma-, X- and L-), was used to simulate the source to drain current. The band-to-band (BTBT) limited off currents, including both the direct and the indirect components, were simulated using TAURUSTM. Our results show that at significantly high gate fields, the current in the III-V materials is largely carried in the heavier L-valleys than the lighter Gamma- valleys, due to the low density of states (DOS) in the Gamma, similar to current conduction in Ge. Moreover, these high mobility materials like InAs, InSb and Ge suffer from excessive BTBT which seriously limits device performance. Large bandgap III-V materials like GaAs exhibit best performance due to an ideal combination of low conductivity effective electron mass and a large bandgap.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"486 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115879552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Local-property analysis for modeling of gate insulator materials","authors":"K. Doi, K. Nakamura, A. Tachibana","doi":"10.1109/IWNC.2006.4570993","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570993","url":null,"abstract":"We have constructed fundamental theories for electronic properties and dielectric breakdown of gate insulator materials in nano-CMOS devices based on the Rigged QED theory and the regional density functional theory. Simulations about dielectric properties and reliability due to these theories have been carried out for SiO<sub>2</sub>, ZrO<sub>2</sub>, HfO<sub>2</sub>, Zr<sub>x</sub>Si<sub>1-x</sub>O<sub>2</sub>, Hf<sub>x</sub>Si<sub>1-x</sub>O<sub>2</sub>, Gd<sub>x</sub>O<sub>y</sub>, La<sub>x</sub>O<sub>y</sub>, and SiO<sub>x</sub>N<sub>y</sub> through the modeling of nano-CMOS system such as crystal and amorphous thin films. Furthermore, we have reported development of the nucleus-electron multiple dynamics program codes following the Rigged QED theory.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Challenges for sub-10 nm CMOS devices","authors":"T. Mogami, H. Wakabayashi","doi":"10.1109/IWNC.2006.4570982","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570982","url":null,"abstract":"Scaling issues of nano-size MOSFETs will be discussed on the basis of sub-10 nm MOSFETs characteristics, which have been developed and confirmed switching characteristics. Understanding device limitations and developing new breakthrough technologies should be required to challenge sub-10-nm CMOS devices.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"77 5‐6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120854706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Deleonibus, B. De Salvo, L. Clavelier, T. Ernst, O. Faynot, T. Poiroux, M. Vinet
{"title":"NanoCMOS devices at the end and beyond the roadmap","authors":"S. Deleonibus, B. De Salvo, L. Clavelier, T. Ernst, O. Faynot, T. Poiroux, M. Vinet","doi":"10.1109/IWNC.2006.4570973","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570973","url":null,"abstract":"Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite carbon, HiK,...), Si based CMOS will be scaled beyond the ITRS as the future system-on-chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, wi ll bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance w ll be the major challenges in the future.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"First-principles evaluations of dielectric constants","authors":"J. Nakamura, Sadakazu Wakui, A. Natori","doi":"10.1109/IWNC.2006.4570994","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570994","url":null,"abstract":"Dielectric properties of ultra-thin Si(111), SiO2, and La2O3(0001) films have been investigated using two methods, internal field method and dipole moment method, based on first-principles ground-state calculations in external electrostatic fields. With increasing the thickness of the Si(111) film, the optical dielectric constant evaluated at the center of the slab converges to the experimental bulk dielectric constant, while the energy gaps of the slabs are still larger than those of corresponding bulks. On the other hand, both the optical and the static dielectric constants of beta-SiO2(0001) films hardly depend on the film thickness and the spatial variation of the local dielectric constant is also very small. It has been found that both the surface effect and the quantum confinement effect are small on ultra-thin beta-SiO2(0001) films. Further, it has been revealed that ultra-thin La2O3(0001) film having a thickness of 1.1 nm possesses a large value of the static dielectric constant (29.2) equivalent to that of bulk.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quo vadis nano-CMOS ?","authors":"T. Skotnicki","doi":"10.1109/IWNC.2006.4570995","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570995","url":null,"abstract":"When I was a student, 25 years ago, one of the hypotheses was that intelligence would appear spontaneously once complexity and speed of a logic system exceed a given level. In the span of last 25 years the CMOS switching frequency has increased X50, the number of transistors per chip X1000, whereas the transistor feature size has decreased X32. In spite of that extraordinary progress, our computers seem all but intelligent. Does it mean that we are still below this magic complexity level? Maybe, but taking into account that CMOS is already today a genuine Nano-technology, there is little room left for improvement. Therefore, will intelligence appear within the remaining 3 or so generations before Nano-CMOS hits the atomic limit? Or maybe we should admit that transistor performance is no longer a key, and targets for CMOS technologies should be refined? If so, what is then THE nano-device we should seek? What is THE nano-technology we should target? In this paper we will deliberate on these and relevant questions (hardly answering ANY).","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123188812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Koyanagi, Y. Yamada, M. Park, T. Fukushima, T. Tanaka
{"title":"Research and development of transistor structure in nano-scale region","authors":"M. Koyanagi, Y. Yamada, M. Park, T. Fukushima, T. Tanaka","doi":"10.1109/IWNC.2006.4570974","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570974","url":null,"abstract":"In this work, new silicon-on-low-k substrate (SOLK) MOSFET and germanium-on-low-k substrate (GOLK) MISFET are proposed. SOLK-MOSFET with metal back-gate was successfully fabricated using wafer bonding method with low-k material as an adhesive. It was shown that the threshold voltage, the on-current, and the off-current are more effectively controlled by the back-gate bias voltage in SOLK-MOSFETs with metal back-gate than in SOI-MOSFETs with buried back-gate. Ge MISFETs were fabricated with HfO2 gate dielectric and W/W2N metal gate which are formed on GOI wafer obtained by a new graded Ge condensation method. Excellent drain current-voltage characteristics and subthreshold characteristics in are obtained in the fabricated GOI-MISFETs.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Material and interface instabilities of high-κ MOS gate dielectric films","authors":"H. Wong, H. Iwai, K. Kakushima","doi":"10.1109/IWNC.2006.4570990","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570990","url":null,"abstract":"It is a general consensus that high-kappa dielectric films, transition metal oxides or rare earth oxides, have to be introduced for future generations of CMOS technology. However, high-kappa gate dielectric materials are found to have many inherent reliability problems because of their fundamental material properties and the instable Si/high-kappa interface. Particularly, the thermal instability, the poor interface properties with silicon, interface silicate layers formation, high interface and oxide trap density, low breakdown field and low mobility have become major concerns on the reliability of the MOS device. This work highlights the issues related to the thermal instability of high-k materials. The instabilities associated with high-kappa dielectric/Si interfaces will be also discussed.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115852436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hiramoto, G. Tsutsui, M. Saitoh, T. Nagumo, T. Saraya
{"title":"Mobility enhancement in (110)-oriented ultra-thin-body single-gate and double-gate SOI MOSFETs","authors":"T. Hiramoto, G. Tsutsui, M. Saitoh, T. Nagumo, T. Saraya","doi":"10.1109/IWNC.2006.4570977","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570977","url":null,"abstract":"Mobility enhancement of both electron and hole is experimentally demonstrated in (110) ultra-thin-body SOI MOSFETs. Single-gate operation and double-gate operation are also compared. Hole mobility enhancement in the single-gate operation is achieved by the suppression of phonon scattering, while electron mobility enhancement in double-gate operation is achieved by volume inversion. Based on the experimental results, the best device structure for highest CMOS circuit performance in future has been discussed.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Defect energy levels in HfO2","authors":"John Robertson, K. Xiong","doi":"10.1109/IWNC.2006.4570991","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570991","url":null,"abstract":"The energy levels of the oxygen vacancy and oxygen interstitial defects in HfO2 are calculated using density functional methods that do not need an empirical bandgap correction. The levels are aligned to those of the Si channel using the known band offsets. The oxygen vacancy gives an energy level nearer the HfO2 conduction band and just above the Si gap, depending on its charge state. It is identified as the main electron trap in HfO2. The oxygen interstitial gives levels just above the oxide valence band.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122258806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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