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2006 IEEE International Conference on Field Programmable Technology最新文献

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Efficient algorithm for functional scheduling in hardware/software co-design 硬件/软件协同设计中高效的功能调度算法
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270296
W. Jigang, T. Srikanthan, Tao Jiao
{"title":"Efficient algorithm for functional scheduling in hardware/software co-design","authors":"W. Jigang, T. Srikanthan, Tao Jiao","doi":"10.1109/FPT.2006.270296","DOIUrl":"https://doi.org/10.1109/FPT.2006.270296","url":null,"abstract":"Task scheduling is one of the crucial steps during functional hardware/software co-design. Due to the possibly concurrent execution of the tasks implemented in hardware, the NP-hard scheduling problem becomes more difficult to solve optimally. In this paper an efficient algorithm is proposed for task scheduling in functional hadware/software co-design. The proposed algorithm assigns the priority for each task combining the information both in the communication penalty and the hardware-only critical path, to enhance the parallelism of the tasks. A large body of experimental results confirm that the proposed algorithm is superior to the most widely used approaches first-come first-schedule(FCFS) and level-by-level schedule (LBLS) in hardware/software scheduling, both for random graphs and some realistic application graphs, without large increase in running time. The improvement over FCFS and LBLS is up to 10% for some random graphs, and it is more significant for FFT application graphs, according to the simulation results on the same types of graphs (under the same assumptions) as in the literature where LBLS is employed","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127874863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os 基于时间复用I/ o的多fpga实现的性能驱动电路双分区算法
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270348
Masato Inagi, Y. Takashima, Yuichi Nakamura, Y. Kajitani
{"title":"A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os","authors":"Masato Inagi, Y. Takashima, Yuichi Nakamura, Y. Kajitani","doi":"10.1109/FPT.2006.270348","DOIUrl":"https://doi.org/10.1109/FPT.2006.270348","url":null,"abstract":"For multi-FPGA systems, the limitation of the number of FPGA I/O-pins is one of the most critical issues. Using time-multiplexed I/Os eases the limitation. While, a signal path through n time-multiplexed I/Os makes the system clock period n + 1 times longer at most. To capture this feature, we introduce a new cost total cut-hopcount. Under the total cut-hopcount, we propose a performance-driven bipartitioning method VIOP. VIOP combines three algorithms, such that i) min-cut partitioning, ii) coarse performance-driven partitioning, and iii) fine performance-driven partitioning. For min-cut and coarse performance-driven partitioning, we employ well-known bipartitioning algorithms CLIP-FM and DUBA, respectively. For fine performance-driven partitioning, we propose a partitioning algorithm CAVP. By VIOP, the average cost was improved by 11.5% compared with the state-of-the-art algorithms","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation 基于反转的硬件高斯随机数生成器:基于分层分割的函数求值案例研究
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270388
Dong-U Lee, R. Cheung, J. Villasenor, W. Luk
{"title":"Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation","authors":"Dong-U Lee, R. Cheung, J. Villasenor, W. Luk","doi":"10.1109/FPT.2006.270388","DOIUrl":"https://doi.org/10.1109/FPT.2006.270388","url":null,"abstract":"We present the design and implementation of a Gaussian random number generator (GRNG) via hierarchical segmentation. Gaussian samples are generated using the inversion method, which involves the evaluation of the inverse Gaussian cumulative distribution function (IGCDF). The IGCDF is highly nonlinear and is evaluated via piecewise polynomial approximations (splines) with a hierarchical segmentation scheme that involves uniform splines and splines with size varying by powers of two. This segmentation approach adapts the spline sizes according to the non-linearity of the function, allowing efficient evaluation of the IGCDF. Bit-widths of the fixed-point polynomial coefficients and arithmetic operators are optimized in an analytical manner to guarantee a precision accurate to one unit in the last place. Our architecture generates 16-bit Gaussian samples accurate to 8.2cr (standard deviations). A pipelined implementation on a Xilinx Virtex-4 XC4LX100-12 FPGA yields 371 MHz and occupies 543 slices, 2 block RAMs, and 2 DSP slices, generating one sample every clock cycle","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An adaptive and predictive architecture for parameterised PIV algorithms 参数化PIV算法的自适应预测体系结构
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270318
Nathalie Bochard, A. Aubert, V. Fresse
{"title":"An adaptive and predictive architecture for parameterised PIV algorithms","authors":"Nathalie Bochard, A. Aubert, V. Fresse","doi":"10.1109/FPT.2006.270318","DOIUrl":"https://doi.org/10.1109/FPT.2006.270318","url":null,"abstract":"Particle image velocimetry (PIV) algorithms aim at flow visualisation and dynamic flow measurement. All existing PIV techniques are computing intensive and are mainly used in critical conditions. For a given experimental environment, several parameters must be set so that PIV algorithm must be parameterised. A dedicated architecture is therefore unsuitable unless it is adaptive. The aim of this work is to prove that our generic and adaptive FPGA-based system for real-time PIV applications previously designed can easily be modified when some parameters vary. From a unique structure and library of resources, the designer adapts the architecture according to the parameters. Time and resource prediction models help the designer to find the most suitable structure before the implementation process and ensure only one implementation without feedback. As a result, the design flow is fast and reliable","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115475463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evaluation of granularity on threshold voltage control in flex power FPGA 柔性电源FPGA中阈值电压控制的粒度评价
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-02-22 DOI: 10.1145/1117201.1117235
M. Hioki, Takashi Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa, H. Koike
{"title":"Evaluation of granularity on threshold voltage control in flex power FPGA","authors":"M. Hioki, Takashi Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa, H. Koike","doi":"10.1145/1117201.1117235","DOIUrl":"https://doi.org/10.1145/1117201.1117235","url":null,"abstract":"The flex power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the flex power FPGA. There is also a trade-off relationship between the static power consumption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127462348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Periodic licensing of FPGA based intellectual property 基于FPGA的知识产权定期许可
2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-02-22 DOI: 10.1145/1117201.1117259
N. Couture, K. Kent
{"title":"Periodic licensing of FPGA based intellectual property","authors":"N. Couture, K. Kent","doi":"10.1145/1117201.1117259","DOIUrl":"https://doi.org/10.1145/1117201.1117259","url":null,"abstract":"This work describes a method of licensing IP on FPGAs based on techniques derived from software licensing schemes. Current software and hardware licensing techniques are described in detail, including a survey of current research in the fields of FPGA security, secure memory technologies, and cryptography. A licensing architecture for FPGA IP is proposed, and an implementation on a Xilinx Vertex 2 FPGA demonstrates that expiration of FPGA based IP can be achieved. Future work includes the development of a hardware architecture for consumer products that supports licensable IP cores as well as their delivery","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131395639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
PowerBit - power aware arithmetic bit-width optimization 功率感知算术位宽优化
2006 IEEE International Conference on Field Programmable Technology Pub Date : 1900-01-01 DOI: 10.1109/FPT.2006.270330
A. A. Gaffar, Jonathan A. Clarke, G. Constantinides
{"title":"PowerBit - power aware arithmetic bit-width optimization","authors":"A. A. Gaffar, Jonathan A. Clarke, G. Constantinides","doi":"10.1109/FPT.2006.270330","DOIUrl":"https://doi.org/10.1109/FPT.2006.270330","url":null,"abstract":"In this paper we present a novel method reducing the dynamic power consumption in FPGA-based arithmetic circuits by optimizing the bit-widths of the signals inside the circuit. The proposed method is implemented in the tool PowerBit, which makes use of macro models parameterized by word-level signal statistics to estimate the circuit power consumption during the optimization process. The power models used take in to account the generation and propagation of signal glitches through the circuit. The bit-width optimization uses a static analysis technique which is capable of providing guaranteed accuracy in the design outputs. We show that, for sample designs implemented on FPGAs that improvements of over 10% are possible for multiple bit-width allocated designs optimized for power compared to designs allocated uniform bit-widths","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
FPT 2006 The End of Indexes [CDROM] FPT 2006索引结束[CDROM]
2006 IEEE International Conference on Field Programmable Technology Pub Date : 1900-01-01 DOI: 10.1109/fpt.2006.270367
{"title":"FPT 2006 The End of Indexes [CDROM]","authors":"","doi":"10.1109/fpt.2006.270367","DOIUrl":"https://doi.org/10.1109/fpt.2006.270367","url":null,"abstract":"You have reached the end of this document.","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125155613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Search Workaround for Users of Acrobat Reader 5 [CDROM] acrobatreader5用户的搜索解决方案[CDROM]
2006 IEEE International Conference on Field Programmable Technology Pub Date : 1900-01-01 DOI: 10.1109/icgrid.2006.310989
{"title":"Search Workaround for Users of Acrobat Reader 5 [CDROM]","authors":"","doi":"10.1109/icgrid.2006.310989","DOIUrl":"https://doi.org/10.1109/icgrid.2006.310989","url":null,"abstract":"All conference CDROMs prepared by Causal Productions contain a search index. The search index allows fast keyword searching of all documents on a CDROM. By default, the search index for Adobe Reader 6 and above is automatically loaded each time the welcome page is viewed. Older Acrobat Reader software (eg. Acrobat Reader 5) is not compatible with the search index created by newer Acrobat software (eg. Adobe Reader 6 and above).","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134425132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel memory architecture for elliptic curve cryptography with parallel modular multipliers 基于并行模乘法器的椭圆曲线密码存储结构
2006 IEEE International Conference on Field Programmable Technology Pub Date : 1900-01-01 DOI: 10.1109/FPT.2006.270306
R. Laue, S. Huss
{"title":"A novel memory architecture for elliptic curve cryptography with parallel modular multipliers","authors":"R. Laue, S. Huss","doi":"10.1109/FPT.2006.270306","DOIUrl":"https://doi.org/10.1109/FPT.2006.270306","url":null,"abstract":"Parallelization of operations is of utmost importance for efficient implementations of public key cryptography algorithms. Taking a clarification of parallelization methods at different abstraction levels of public key algorithms as a foundation, we propose a novel memory architecture for elliptic curve implementations with multiple modular multiplier units. This architecture is well-suited for different algorithms over GF(P) to be implemented on FPGAs. It allows the execution time to scale with the number of modular multipliers and features nearly no overhead compared to the mere runtime of the multipliers. The advantages of this distributed memory architecture is demonstrated by means of two different EC point multiplications algorithms","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133471620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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