Yiqun Zhu, B. Hayes-Gill, S. Morgan, Nguyen C. Hoang
{"title":"An FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow camera","authors":"Yiqun Zhu, B. Hayes-Gill, S. Morgan, Nguyen C. Hoang","doi":"10.1109/FPT.2006.270328","DOIUrl":"https://doi.org/10.1109/FPT.2006.270328","url":null,"abstract":"This paper presents an FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow imaging application. The proposed platform consists of a Xilinx Spartan-3 FPGA device, Analog Device 125MSPS, 14-bit ADCs, Cypress 167MHz, 2Mtimes18bits QDR memory, and a highspeed (480MHz) USB 2.0 link. In this platform, the FPGA device not only acts as controllers of the ADCs, QDR memory and the USB link, but also provides a high-speed FFT processing capability, which is a key computation in laser Doppler blood flowmetry. Based on this platform, with the number of FFT points of 1024, a full-field laser Doppler blood flowmetry imaging system can deliver flow image frames (256x256 pixels) every 1.7 seconds, which is seven times faster than existing systems","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
João Bispo, I. Sourdis, João MP Cardoso, S. Vassiliadis
{"title":"Regular expression matching for reconfigurable packet inspection","authors":"João Bispo, I. Sourdis, João MP Cardoso, S. Vassiliadis","doi":"10.1109/FPT.2006.270302","DOIUrl":"https://doi.org/10.1109/FPT.2006.270302","url":null,"abstract":"Recent intrusion detection systems (IDS) use regular expressions instead of static patterns as a more efficient way to represent hazardous packet payload contents. This paper focuses on regular expressions pattern matching engines implemented in reconfigurable hardware. A nondeterministic finite automata (NFA) based implementation was presented, which takes advantage of new basic building blocks to support more complex regular expressions than the previous approaches. The methodology is supported by a tool that automatically generates the circuitry for the given regular expressions, outputting VHDL representations ready for logic synthesis. Furthermore, techniques to reduce the area cost of our designs and maximize performance when targeting FPGAs were included. Experimental results show that our tool is able to generate a regular expression engine to match more than 500 IDS regular expressions (from the Snort ruleset) using only 25K logic cells and achieving 2 Gbps throughput on a Virtex2 and 2.9 on a Virtex4 device. Concerning the throughput per area required per matching non-meta character, our design is 3.4 and 10 times more efficient than previous ASIC and FPGA approaches, respectively","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126621039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sudarshan Banerjee, E. Bozorgzadeh, Juanjo Noguera, N. Dutt
{"title":"Minimizing peak power for application chains on architectures with partial dynamic reconfiguration","authors":"Sudarshan Banerjee, E. Bozorgzadeh, Juanjo Noguera, N. Dutt","doi":"10.1109/FPT.2006.270326","DOIUrl":"https://doi.org/10.1109/FPT.2006.270326","url":null,"abstract":"Power consumption is a key concern on modern reconfigurable architectures. In this paper, we address the problem of minimizing peak power while mapping application task chains onto reconfigurable architectures with partial dynamic reconfiguration capability. Our proposed methodology minimizes peak power for a given timing constraint. It is based on detailed data-parallelism considerations to ensure that tight timing constraints are met. Our methodology generates physically placed task execution schedules and includes selection of a suitable number of data-parallel instances for each task, a suitable clock frequency, and execution workload for each task instance. Case studies on real image-filtering applications demonstrate that our approach results in significant peak power savings (between 40%-50%) for tight as well as relaxed timing constraints","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115983539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA core watermarking based on power signature analysis","authors":"Daniel Ziener, J. Teich","doi":"10.1109/FPT.2006.270313","DOIUrl":"https://doi.org/10.1109/FPT.2006.270313","url":null,"abstract":"This paper introduces a new method to watermark FPGA cores where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method, where the signature is extracted in this way. The authors were able to sign cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. The power watermarking method works with all types of FPGAs, but with Xilinx FPGAs, the watermarking algorithms and the signature can be integrated into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. A detection algorithm was introduced which can decode the signature from a voltage trace with high probability. Additionally, a second algorithm is introduced which improves the detection probability in case of considerable noise sources. Using this algorithm, it is possible to decode the signature even if other cores operate on the same device at the same time","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"1037 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. A. S. Marcos, M. Garrido, M. López-Vallejo, C. López-Barrio
{"title":"Automated design space exploration of FPGA-based FFT architectures based on area and power estimation","authors":"M. A. S. Marcos, M. Garrido, M. López-Vallejo, C. López-Barrio","doi":"10.1109/FPT.2006.270303","DOIUrl":"https://doi.org/10.1109/FPT.2006.270303","url":null,"abstract":"In this paper a tool aimed at generating fast Fourier transform (FFT) cores targeting FPGA platforms was presented. The tool is able to generate different pipelined architectures of the FFT that provide different points of the design space: from high performance to low area implementations. The user can select the most suitable architecture based on a broad set of configuration parameters, as they are the number of points, sample size, truncation, etc. Moreover, a set of accurate estimators has been implemented to allow the designer an early and quick design space exploration before synthesizing the core. Experimental results validate our approach and provide significant measurements about the accuracy of the estimation and the tool execution time","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125301311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A leakage aware design methodology for power-gated programmable architectures","authors":"N. Subramanian, Rajarshee P. Bharadwaj, D. Bhatia","doi":"10.1109/FPT.2006.270333","DOIUrl":"https://doi.org/10.1109/FPT.2006.270333","url":null,"abstract":"One popular technique to deal with increasing leakage current in modern FPGAs is to group logic into sleeper cells and isolate them from power rails whenever they are inactive in time and space. However, such architectures demand novel methodology to effectively layout the design, so that maximum sleeper cells can be shut down. In this work, we present a slicing tree based simulated annealing methodology that grooms the various blocks of a design, so that they can be put into power-down mode either in temporal or spatial domain. Our technique nicely fits into a power-aware design flow targeting standby/portable applications where substantial portion of the design sits idle for a long period of time. We also propose a novel technique to include BRAMs into the presented methodology. Our experiments shows up to a maximum 43% of leakage savings in some benchmarks","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132308503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Eeckhaut, M. Christiaens, D. Stroobandt, V. Nollet
{"title":"Optimizing the critical loop in the H.264/AVC CABAC decoder","authors":"H. Eeckhaut, M. Christiaens, D. Stroobandt, V. Nollet","doi":"10.1109/FPT.2006.270301","DOIUrl":"https://doi.org/10.1109/FPT.2006.270301","url":null,"abstract":"This paper presents an innovative hardware implementation of the H.264/AVC CABAC binary arithmetic decoder and context modeler capable of decoding one symbol per clock cycle at high clock frequencies while maintaining a slim hardware footprint. This was achieved by substantially decreasing the latency of the central feedback loop through extensive use of speculative prefetching and aggressive pipelining. Actual synthesis results targeted at the state-of-the-art FPGA families show that our approach results in a fast and compact IP core, ideal for a SoC H.264/AVC implementation","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134367147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Invited Keynote 2: Applications of programmable logic in modern particle physics experiments","authors":"G. Hall","doi":"10.1109/FPT.2006.270376","DOIUrl":"https://doi.org/10.1109/FPT.2006.270376","url":null,"abstract":"The newest generation of particle physics experiments is in the final stages of construction in CERN, Geneva in preparation for data taking at a new accelerator, the Large Hadron Collider (LHC), which will be the world’s highest energy machine. These experiments are immensely challenging to build for several reasons and rely heavily on their electronic systems, which are as advanced as the rapid pace of technology evolution will permit. Most of each experiment will be subjected to intense radiation fluxes from the unprecedented rate of interactions between the beams of colliding protons, and to study the new physics which is expected to be discovered, rare events need to be captured for complete analysis in an unbiased way. However, most of the data registered by the detectors must be discarded, simply because the volume and rates are so high that the computer systems cannot record to permanent storage sufficiently fast. The ability to do select extremely rare events will be crucial to the success of the LHC physics programme. Recent developments of FPGA devices have been exploited to maximise the flexibility and power of the data analysis systems which are being implemented. The motivation for the experiments and a brief summary of the most important detector systems of one of them, CMS the Compact Muon Solenoid experiment will be presented, with more detailed explanations of some of the electronic systems and where, why and how programmable logic is so important to them.","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Invited Keynote 1: Closing the gap between FPGAs and ASICs","authors":"Jonathan Rose","doi":"10.1109/FPT.2006.270375","DOIUrl":"https://doi.org/10.1109/FPT.2006.270375","url":null,"abstract":"","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generating hardware from OpenMP programs","authors":"Y. Y. Leow, C. Ng, W. Wong","doi":"10.1109/FPT.2006.270297","DOIUrl":"https://doi.org/10.1109/FPT.2006.270297","url":null,"abstract":"Various high level hardware description languages have been invented for the purpose of improving the productivity in the generation of customized hardware. Most of these languages are variants, usually parallel versions, of popular software programming languages. In this paper, we describe our effort to generate hardware from OpenMP, a software parallel programming paradigm that is widely used and tested. We are able to generate FPGA hardware from OpenMP C programs via synthesizable VHDL and Handel-C. We believe that the addition of this medium-grain parallel programming paradigm will bring additional value to the repertoire of hardware description languages","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}