{"title":"3D integrated circuit using large grain polysilicon film","authors":"V.W.C. Chan, P. Chan, M. Chan","doi":"10.1109/ICSICT.2001.981424","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981424","url":null,"abstract":"3-D CMOS IC technology built on two layers of large grain polysilicon is presented. These stacked layers are vertically interconnected allowing shorter interconnect to improve the logic speed. The large grain polysilicon-on-insulator (LPSOI) film is formed by the recrystallization of amorphous silicon through Metal Induced Lateral Crystallization (MILC). The crystallization region obtained can cover multiple transistors and the grain size is much larger than the transistor size. An oxide layer separates two layers of devices and forms an interlayer dielectric. The electrical performance of the LPSOI devices is presented. Inverters, ring-oscillators and shift registers further confirm that the recrystallized techniques forming the 3-D structures are feasible.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel accelerometer using MOS ring oscillators","authors":"Zhang Zhaohua, Liu Litian","doi":"10.1109/ICSICT.2001.982027","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982027","url":null,"abstract":"Piezoresistive silicon accelerometers have many excellent performance characteristics such as high sensitivity, high reliability and low cost. In this paper, a novel piezoresistive silicon accelerometer using MOS ring oscillators is described and analysed. This accelerometer consists of two MOS ring oscillators, a mixer and a filter. Using a ring oscillator, the input acceleration changed into digital frequency output signal, this makes it easy to be used in digital world. The mechanical structure of this accelerometer is made up of one mass and four beams. Such structure can not only decrease cross-axis sensitivity, but also utilize the strain caused by input acceleration. Using finite-element analysis (FEA) software, we did strain simulation in order to analyse the stress distribution. The result of finite-element method simulation accorded with theory analysis very much. The MOS ring oscillator consists of an odd number of inverting gates connected in a ring and can be realized by CMOS, NMOS or PMOS circuits. The different kinds of MOS ring oscillator have different performances. Since MOS FET can realize the function of mixing frequency, the mixer is made up of MOS FET.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126266374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shifei Jin, C. Peiyi, Li Chen, Luo Guangli, Zhu Peiyu, H. Wentao, T. Peihsin, Liang Shurong, Zhen Yunfen, Guo Weilian
{"title":"Manufacture of SiGe HMOSFET","authors":"Shifei Jin, C. Peiyi, Li Chen, Luo Guangli, Zhu Peiyu, H. Wentao, T. Peihsin, Liang Shurong, Zhen Yunfen, Guo Weilian","doi":"10.1109/ICSICT.2001.981551","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981551","url":null,"abstract":"The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed devices have led to increased interest in silicon-based heterojunction field-effect transistors. Here we present a kind of strained SiGe-channel P-MOSFET which can offer better performance compared to the Si device. When applying to the sample with W/L value of 14/7, a 30% improvement can be achieved in transconductance.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126395108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The quantum effects in MOSFET's: threshold voltage creep","authors":"Wu-yun Quan, D.M. Kim","doi":"10.1109/ICSICT.2001.982040","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982040","url":null,"abstract":"The phenomenon that the inversion charge is sublinear to gate voltage is presented and modeled via V/sub TH/-creep. V/sub TH/-creep can be as large as 50% of the onset threshold voltage, showing its importance in modeling the I-V characteristics of MOSFETs.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126398532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MEMS technology for biomedical applications","authors":"D. Polla","doi":"10.1109/ICSICT.2001.981417","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981417","url":null,"abstract":"MEMS technology is enabling a wide variety of biomedical systems. This technology is now integrating microscale sensors, actuators, microfluidics, micro-optics, and structural elements with computation, communications, and controls for application to medicine for the improvement of human health. Derived from the microfabrication technology used to make integrated circuits, bioMEMS is expected to revolutionize the way medicine is practiced and delivered. This paper presents an introductory overview of three exciting new opportunity areas for bioMEMS in medicine. These are surgical microsystems (intelligent micro-invasive surgical tools), diagnostic microsystems (biochips and related micro-instrumentation), and therapeutic micro-systems (health care management systems). Some representative examples based on work carried out at the University of Minnesota (USA) are presented, including (1) MEMS in precision surgery-ophthalmology; (2) MEMS in biomolecular recognition; and (3) MEMS in autonomous therapy management systems-micro-pumps for drug delivery. Selected human clinical trials of the application of BioMEMS are presented.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126440156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low phase noise and high output power VCO design for a fully integrated GSM RF transceiver","authors":"L.B. Li","doi":"10.1109/ICSICT.2001.981461","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981461","url":null,"abstract":"Demonstrates the 900 MHz transmit VCO (TX VCO) design for fully integrated GSM transceiver to meet volume production requirements. On-chip varactors and package inductors were used in the VCO design. The phase noise of the VCO is -163 dBc/Hz at 20 MHz frequency offset and output power is 10 dBm.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126514964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrical characteristics of a new lateral trench electrode IGBT for smart power IC","authors":"E. Kang, S. Moon, M. Sung","doi":"10.1109/ICSICT.2001.981439","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981439","url":null,"abstract":"A new small sized Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) was proposed to improve characteristics of the conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire Electrode of LTEIGBT was replaced with trench-type electrode. The LTEIGBT was designed so that the width of the device was no more than 19/spl mu/m. Latch-up current densities of the proposed LTEIGBT increased 10 and 2.3 times more than those of the conventional LIGBT and LTIGBT. Forward blocking voltage of the LTEIGBT was 130V. Conventional LIGBT and LTIGBT of the same size were 60V and 100V, respectively. Because the proposed LTEIGBT was constructed of trench-type electrodes, the electric field moved toward the trench-oxide layer and punch-through breakdown finally occurred.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New global insight in ultra-thin oxide reliability using accurate experimental methodology and theoretical modeling","authors":"E. Wu, J. Suñé","doi":"10.1109/ICSICT.2001.982071","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982071","url":null,"abstract":"We critically examine several important aspects concerning ultra-thin oxide reliability. Time- or charge-to-breakdown (T/sub BD//Q/sub BD/) measurements with high statistical accuracy are carried out over a wide range of oxide thickness (T/sub ox/), voltages, temperatures, and test structures. Thickness dependence of Weibull slopes and its physical interpretation based on a simple analytic model are reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods of long-term module stress and area scaling techniques. In the context of voltage-dependent voltage acceleration, we resolve various seemingly contradicting and confusing observations such as the strong temperature dependence of oxide breakdown observed on ultra-thin oxides, temperature-independent voltage acceleration at a fixed T/sub BD/, and non-Arrhenius temperature dependence found on ultra-thin oxides. Using a newly developed kinetic approach for oxide breakdown, we propose a two-step hydrogen model as an alternative to explain the experimental observations on voltage-dependent voltage acceleration and temperature dependence of oxide breakdown.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Mori, N. Tanabe, A. Seike, H. Takeuchi, J. Yamada, T. Miwa, H. Koike, Y. Maejima, T. Tatsumi, S. Kobayashi, T. Nakura, H. Sugiyama, N. Kasai, T. Hase, H. Hada, H. Toyoshima
{"title":"A high-endurance 96-Kbit FeRAM embedded in a smart card LSI using Ir/IrO2/PZT(MOCVD)/Ir ferroelectric capacitors","authors":"H. Mori, N. Tanabe, A. Seike, H. Takeuchi, J. Yamada, T. Miwa, H. Koike, Y. Maejima, T. Tatsumi, S. Kobayashi, T. Nakura, H. Sugiyama, N. Kasai, T. Hase, H. Hada, H. Toyoshima","doi":"10.1109/ICSICT.2001.981454","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981454","url":null,"abstract":"We have developed a logic-embedded 96-Kbit FeRAM macro that has low-voltage operation and high-endurance features for smart card applications. The smart card LSI was fabricated using a 0.35 /spl mu/m-standard CMOS process with 3-level metallization and CMVP ferroelectric capacitors. The operation of the chip was confirmed at voltages from 2.7 to 5.5 V with 2.5 MHz clock cycle. By using Ir-based top and bottom electrodes, the fatigue endurance of the FeRAM was improved, which was confimed in burn-in tests. No failed bits were observed at accelerated conditions with 5.5 V and 150/spl deg/C after 10/sup 8/ fatigue cycles.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130436538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"1 /spl mu/m CMOS programmable surface acoustic wave filter integrated circuit","authors":"Ying Chen, Dazhong Zhu, Yuan-Chuan Wang","doi":"10.1109/ICSICT.2001.982095","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982095","url":null,"abstract":"In this paper a 8-bit 1 /spl mu/m CMOS programmable surface acoustic wave filter integrated circuit is introduced and fabricated. It can be used for sampling, weighting, controlling and summing of both SAW delay lines and SAW IDTs in multi-chip module (MCM) programmable SAW filters. The circuit of each bit consists of two sampling capacitances, which are constructed in a sandwich structure of two layers of Al and one layer of polysilicon, and two high transconductance MOSFETs with a high W/L ratio. Its programmability arises from the change of on-resistance of the output MOSFET with weighting voltage in its gate. The summing function is realized by the connection of the output terminals of each bit. After testing, an 18.68 dB insertion loss and a 16.31 dB on/off ratio are obtained at 35.5 MHz. This IC can realize sampling, weighting, controlling and summing of the SAW signal within the frequency range from 15 MHz to 200 MHz with an acceptable insertion loss (-7.94 dB /spl sim/-20 dB) and on/off ratio (7 dB /spl sim/18 dB).","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}