2008 IEEE International Conference on Computer Design最新文献_第2页

Energy-delay tradeoffs in 32-bit static shifter designs 32位静态移位器设计中的能量延迟权衡

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751926

Steve Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, D. Harris, D. Patil

引用次数: 13

Energy-aware opcode design 节能操作码设计

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751918

Balaji V. Iyer, Jason A. Poovey, T. Conte

引用次数: 0

Improved combined binary/decimal fixed-point multipliers 改进的组合二进制/十进制定点乘法器

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751845

Brian J. Hickmann, M. Schulte, M. A. Erle

引用次数: 11

The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks 2D DBM:对于片上网络来说，简单的2D网格拓扑是一个有吸引力的替代方案

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751905

R. Sabbaghi‐Nadooshan, M. Modarressi, H. Sarbazi-Azad

引用次数: 11

Reversi: Post-silicon validation system for modern microprocessors 用于现代微处理器的后硅验证系统

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751878

I. Wagner, V. Bertacco

{"title":"Reversi: Post-silicon validation system for modern microprocessors","authors":"I. Wagner, V. Bertacco","doi":"10.1109/ICCD.2008.4751878","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751878","url":null,"abstract":"Verification remains an integral and crucial phase of todaypsilas microprocessor design and manufacturing process. Unfortunately, with soaring design complexities and decreasing time-to-market windows, todaypsilas verification approaches are incapable of fully validating a microprocessor before its release to the public. Increasingly, post-silicon validation is deployed to detect complex functional bugs in addition to exposing electrical and manufacturing defects. This is due to the significantly higher execution performance offered by post-silicon methods, compared to pre-silicon approaches. Validation in the post-silicon domain is predominantly carried out by executing constrained-random test instruction sequences directly on a hardware prototype. However, to identify errors, the state obtained from executing tests directly in hardware must be compared to the one produced by an architectural simulation of the designpsilas golden model. Therefore, the speed of validation is severely limited by the necessity of a costly simulation step. In this work we address this bottleneck in the traditional flow and present a novel solution for post-silicon validation that exposes its native high performance. Our framework, called Reversi, generates random programs in such a way that their correct final state is known at generation time, eliminating the need for architectural simulations. Our experiments show that Reversi generates tests exposing more bugs faster, and can speed up post-silicon validation by 20x compared to traditional flows.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Exploiting producer patterns and L2 cache for timely dependence-based prefetching 利用生产者模式和二级缓存进行及时的基于依赖的预取

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751935

C. Lim, G. Byrd

引用次数: 6

Energy-precision tradeoffs in mobile Graphics Processing Units 移动图形处理单元中的能量-精度权衡

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751841

Jeff Pool, A. Lastra, Montek Singh

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引用次数: 37

Gate planning during placement for gated clock network 门控时钟网络布置期间的门规划

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751851

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu

{"title":"Gate planning during placement for gated clock network","authors":"Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu","doi":"10.1109/ICCD.2008.4751851","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751851","url":null,"abstract":"Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous approaches still have a significant weakness. That is, they usually construct a gated clock tree after cell placement, i.e., cell placement is performed without considering clock gating and may generate a solution unfriendly to subsequent gated clock tree construction. As a result, the control gates inserted in the tree construction is very likely to cause cell overlap. Even though the overlap can be eventually removed in placement legalization, remarkable wirelength/power overhead is incurred. In this paper, we propose a gate planning technique which is integrated with a partition-based cell placer. During cell placement, the planning judiciously inserts clock gates based on power estimation. In addition, pseudo edges are inserted between clock gates and registers in order to reduce clock wirelength and enable long shut-off periods. At the end, when a relatively detailed placement is obtained, a post-processing is performed to degrade the inefficient clock gates to clock buffers. We compared our approach with recent previous works on ISCAS89 benchmark circuits. Our method reduces the clock tree wirelength and power by 22.06% and 40.80%, respectively, with a very limited increase on signal nets wirelength and power compared with the conventional (register-oblivious) placement. The results also indicate that our algorithm outperforms the clock-gating-oblivious placement on power reduction and performance improvement.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125237064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters 具有非均匀离散参数的模拟电路尺寸的随机和伪梯度方法

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751860

Michael Pehl, Tobias Massier, H. Graeb, Ulf Schlichtmann

引用次数: 6

Is there always performance overhead for regular fabric? 普通织物是否总是有性能开销?

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751916

Yi-Wei Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, D. Kasprowicz

引用次数: 23