Is there always performance overhead for regular fabric?

Abstract

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.