2008 IEEE International Conference on Computer Design最新文献

Synthesis of parallel prefix adders considering switching activities 考虑切换活动的并行前缀加法器的综合

2008 IEEE International Conference on Computer Design Pub Date : 2008-12-01 DOI: 10.1109/ICCD.2008.4751892

T. Matsunaga, S. Kimura, Y. Matsunaga

引用次数: 6

A fine-grain dynamic sleep control scheme in MIPS R3000 MIPS R3000中的一种细粒度动态睡眠控制方案

2008 IEEE International Conference on Computer Design Pub Date : 2008-12-01 DOI: 10.1109/ICCD.2008.4751924

N. Seki, Lei Zhao, J. Kei, D. Ikebuchi, Y. Kojima, Y. Hasegawa, H. Amano, Toshihiro Kashima, S. Takeda, T. Shirai, M. Nakata, K. Usami, T. Sunata, J. Kanai, M. Namiki, Masaaki Kondo, Hiroshi Nakamura

引用次数: 38

Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective SMT和CMP架构中线程级推测的效率——性能、功率和热的观点

2008 IEEE International Conference on Computer Design Pub Date : 2008-12-01 DOI: 10.1109/ICCD.2008.4751875

Venkatesan Packirisamy, Yangchun Luo, W. Hung, Antonia Zhai, P. Yew, Tin-fook Ngai

{"title":"Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective","authors":"Venkatesan Packirisamy, Yangchun Luo, W. Hung, Antonia Zhai, P. Yew, Tin-fook Ngai","doi":"10.1109/ICCD.2008.4751875","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751875","url":null,"abstract":"Computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000psilas. However, because of the lack of compilers and other related software technologies, most of the general-purpose applications today still cannot take advantage of such architectures to improve their performance. Thread-level speculation (TLS) has been proposed as a way of using these multi-threaded architectures to parallelize general-purpose applications. Both simultaneous multithreading (SMT) and chip multiprocessors (CMP) have been extended to implement TLS. While the characteristics of SMT and CMP have been widely studied under multi-programmed and parallel workloads, their behavior under TLS workload is not well understood. The TLS workload due to speculative nature of the threads which could potentially be rollbacked and due to variable degree of parallelism available in applications, exhibits unique characteristics which makes it different from other workloads. In this paper, we present a detailed study of the performance, power consumption and thermal effect of these multithreaded architectures against that of a Superscalar with equal chip area. A wide spectrum of design choices and tradeoffs are also studied using commonly used simulation techniques. We show that the SMT based TLS architecture performs about 21% better than the best CMP based configuration while it suffers about 16% power overhead. In terms of Energy-Delay-Squared product (ED2), SMT based TLS performs about 26% better than the best CMP based TLS configuration and 11% better than the superscalar architecture. But the SMT based TLS configuration, causes more thermal stress than the CMP based TLS architectures.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131731822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A floating-point fused dot-product unit 一种浮点融合点积单位

2008 IEEE International Conference on Computer Design Pub Date : 2008-11-10 DOI: 10.1109/ICCD.2008.4751896

H. Saleh, E. Swartzlander

引用次数: 60

Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities 具有扫描和复位能力的面积和功率延迟高效状态保持脉冲触发触发器

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751857

K. Shi

引用次数: 3

On-chip high performance signaling using passive compensation 采用无源补偿的片上高性能信号

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751859

Yulei Zhang, Ling Zhang, A. Tsuchiya, M. Hashimoto, Chung-Kuan Cheng

{"title":"On-chip high performance signaling using passive compensation","authors":"Yulei Zhang, Ling Zhang, A. Tsuchiya, M. Hashimoto, Chung-Kuan Cheng","doi":"10.1109/ICCD.2008.4751859","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751859","url":null,"abstract":"To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lines) is proposed and optimized in this paper. Firstly, we use passive compensation and repeated transceivers composed by sense amplifier and inverter chain to compensate the distortion and attenuation of on-chip T-lines. Secondly, an optimization flow for designing this scheme based on eye-diagram prediction and sequential quadratic programming (SQP) is proposed. This flow is employed to study the latency, power dissipation and throughput performance of the new global wiring scheme as the technology scales from 90nm to 22nm. Compared with conventional repeater insertion methods, our experimental results demonstrate that, at 22nm technology node, this new scheme reduces the normalized delay by 85.1%, the normalized energy consumption by 98.8%. Furthermore, all the performance metrics are scalable as the technology advances, which makes this new signaling scheme a potential candidate to break the “interconnect wall” of digital system performance.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123682557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Power-state-aware buffered tree construction 电力状态感知缓冲树结构

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751835

I. Jiang, Ming-Hua Wu

引用次数: 2

Probabilistic error propagation in logic circuits using the Boolean difference calculus 用布尔差分法研究逻辑电路中的概率误差传播

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751833

Nasir Mohyuddin, E. Pakbaznia, Massoud Pedram

引用次数: 106

Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design 面向软硬件协同设计的虚拟指令集模拟器的定量全局数据流分析

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751888

Carsten Gremzow

引用次数: 3

Highly reliable A/D converter using analog voting 采用模拟投票的高可靠A/D转换器

2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751882

A. Namazi, S. Askari, M. Nourani

引用次数: 12