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CALMOS : A Portable Software System for the Automatic and Interactive Layout of MOS/LSI 一种用于MOS/LSI自动交互布局的便携式软件系统
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600095
H. Beke, W. Sansen
{"title":"CALMOS : A Portable Software System for the Automatic and Interactive Layout of MOS/LSI","authors":"H. Beke, W. Sansen","doi":"10.1109/DAC.1979.1600095","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600095","url":null,"abstract":"CALMOS (Computer Aided Layout of MOS) is a computer system for the layout of custom MOS/LSI circuits. Starting with a standard cell library and a simple circuit connectivity description, the program performs various automatic and/or interactive procedures such as initial placement, assignment of equivalent and equipotential pins, optimization of the placement, prerouting, routing, routing compression, fan in fan out and crosstalk verification and circuit verification. The database has reentrant properties such that a designer can step through the system and try out different possibilities. After each step the results are immediately available and can be compared with previous outputs. This on-line optimization avoids multiple rerunning of the task and will also yield a better chip minimization. CALMOS is written in standard FORTRAN and only needs 32K (16 bit) of memory (300 cell version) together with simple overlay facilities. As a result it can easily be installed on almost any existing computersystem. Because of this portability, the algorithmic strength and the modularity of CALMOS is successfully combined with the on-line interactive facilities of existing graphic systems. Such an integration which is actually under development, will allow for the creation of a stand alone integrated minicomputer based LSI design system. It will be based on a common design language and include logic simulation, layout, circuit analysis, design rule checking, logic verification and test pattern generation.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134031833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Instruction Set Processor Specifications for Simulation, Evaluation, and Synthesis 指令集处理器规格模拟，评估和综合
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600090
M. Barbacci
{"title":"Instruction Set Processor Specifications for Simulation, Evaluation, and Synthesis","authors":"M. Barbacci","doi":"10.1109/DAC.1979.1600090","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600090","url":null,"abstract":"Formal descriptions of digital computers have been used traditionally for pedagogical purposes [Barbacci75]. Recent developments however, illustrate that a formal computer description is highly useful in the simulation, evaluation, and synthesis of computers and other digital systems. In this paper we shall review the use of the ISP notation [Bell71, Barbacci76, Barbacci77] at Carnegie-Mellon University. The paper is organized into three sections that deal with the language, its use in the simulation and evaluation of computer architectures, and finally, its use in computer aided design. I this paper we emphasize the commonality between these seemingly disjoint application. The reader is invited to consult the specific references for additional information of any particular subject.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134514980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Silicon Compilation-A Hierarchical Use of PLAs 硅编译- pla的层次化应用
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600126
R. Ayres
{"title":"Silicon Compilation-A Hierarchical Use of PLAs","authors":"R. Ayres","doi":"10.1109/DAC.1979.1600126","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600126","url":null,"abstract":"This paper proposes a way to compile a silicon layout directly from synchronous logic specification. The motivation for introducing compilation into the silicon world comes from its extreme success in the software world. As we see silicon area increasing and circuit complexity increasing, we might feel much in common with the early day programmers who faced increasing memory availability along with increasing program complexity.\u0000 Software and hardware revolve around the same basic concern: The software designer lays out a one dimensional array of memory whereas the integrated circuit designer lays out a two dimensional area of silicon. In each case, various constraints must be satisfied in order to obtain a working product. In addition, both efforts involve lots of modification.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125806233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Hierarchical Placement Procedure with a Simple Blocking Scheme 一种具有简单阻塞方案的分层放置程序
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600082
S. Murai, Hiroo Tsuji, M. Kakinuma, K. Sakaguchi, C. Tanaka
{"title":"A Hierarchical Placement Procedure with a Simple Blocking Scheme","authors":"S. Murai, Hiroo Tsuji, M. Kakinuma, K. Sakaguchi, C. Tanaka","doi":"10.1109/DAC.1979.1600082","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600082","url":null,"abstract":"The outline of a hierarchical placement procedure utilizing a simple blocking scheme is described with the results of the application to the DSA-MOS gate arrays. Indirect clustering value is introduced for the blocking, i.e. grouping of modules under block size restriction. The system including the procedure has been successfully applied to the design of MOS gate arrays with effectively no manual assistance.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"56 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122234727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An Introduction to the N. mPc Design Environment N. mPc设计环境简介
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600159
F. Parke
{"title":"An Introduction to the N. mPc Design Environment","authors":"F. Parke","doi":"10.1109/DAC.1979.1600159","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600159","url":null,"abstract":"N. mPc, a design tool for multi-processor systems, consists of six components which work together to produce functional register transfer level simulations of multiple processor, heterogeneous target systems. A meta assembler allows the user to specify the format, nmemonics, and associated bit patterns of target instruction sets. Instruction nmemonics are mapped into bit strings and output in a machine independent control/memory allocation graph. A generalized linking loader resolves the machine dependent aspects of assembler output graphs, links, and allocates the resulting image to physical memory according to user specified strategies. A hardware description language , ISP', compiler is used to translate processor and interconnection element descriptions into executable code. This code, the linking loader outputs, and a description of the target system topology are linked by an Ecologist and Simulated Memory Processor into a simulation model which runs under the control of a Runtime Package. The Runtime Package consists of a Command Interpreter, Kernel, and Simulated Memory Manager. The Kernel and Command Interpreter permit interactive control and monitoring of simulations. The Simulated Memory Manager supervises the simulated memory contents, available physical memory, and mass storage to optimize the performance of the simulation. N. mPc is implemented on a PDP-11 system under the UNIX operating system and is currently undergoing system test and evaluation.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The CMU Design Automation System - An Example of Automated Data Path Design CMU设计自动化系统-自动化数据路径设计的一个例子
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1145/62882.62945
A. C. Parker, D. E. Thomas, D. Siewiorek, M. Barbacci, L. Hafer, G. Leive, Jin H. Kim
{"title":"The CMU Design Automation System - An Example of Automated Data Path Design","authors":"A. C. Parker, D. E. Thomas, D. Siewiorek, M. Barbacci, L. Hafer, G. Leive, Jin H. Kim","doi":"10.1145/62882.62945","DOIUrl":"https://doi.org/10.1145/62882.62945","url":null,"abstract":"This paper illustrates the methodology of the CMU Design Automation system by presenting an automated design of the PDP-8/E data paths from a functional description. This automated design (using synthesis techniques) is compared both to DEC's implementation and the Intersil single chip implementation.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130467111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
A New Circuit Placement Program for FET Chips 一种新的FET芯片电路布置方案
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600096
K. Lallier, R. Jackson
{"title":"A New Circuit Placement Program for FET Chips","authors":"K. Lallier, R. Jackson","doi":"10.1109/DAC.1979.1600096","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600096","url":null,"abstract":"A new solution to the problem of automated placement of FET circuits has been implemented. This new approach automatically realizes a global solution to the problem yielding circuit location, circuit orientation, all cross column wires and blanks between circuits, thus eliminating many of the most tedious and error prone steps in physical design. The technique is based upon \"natural selection\" and obtains a solution using a series of sweeps through the columns evolving circuit position and cross column wiring assignments together. Scoring is done to minimize column peaks. This paper describes the novel aspects of the program including the control techniques, models and approach used. The program was developed for IBM's internal use in design.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124135288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computer Simulation of Foliage Shading in Building Energy Loads 建筑能耗中树叶遮阳的计算机模拟
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600101
M. Schiler, D. Greenberg
{"title":"Computer Simulation of Foliage Shading in Building Energy Loads","authors":"M. Schiler, D. Greenberg","doi":"10.1109/DAC.1979.1600101","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600101","url":null,"abstract":"The calculation of building thermal loads using the computer has been an accepted practice for several years. A substantial amount of research and theoretical investigation has been expended in attempts to accurately quantify a building's thermal behavior. A number of existing simulation packages acceptably model this behavior.1,2,3,4,5,6\u0000 The advantages of simulation are obvious, not only for the predictive information with respect to operating costs or fuel consumption, but as a potential aid for preliminary design. The influence and tradeoffs of a large number of design variables such as siting, orientation, window area, thermal resistivity, surface/volume ratios, and cost can all be examined at an early stage in the design process.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130730849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Hybrid Scheduling Technique for Hierarchical Logic Simulators or "Close Encounters of the Simulated Kind" 层次逻辑模拟器的混合调度技术或“模拟类近距离接触”
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600115
W. Sherwood
{"title":"A Hybrid Scheduling Technique for Hierarchical Logic Simulators or \"Close Encounters of the Simulated Kind\"","authors":"W. Sherwood","doi":"10.1109/DAC.1979.1600115","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600115","url":null,"abstract":"Advancing circuit complexity in LSI technology has brought about an ever growing need for more powerful Computer Aided Design tools. Verification of an IC design through simulation is mandatory to avoid costly mask iterations and delays in product introduction due to design errors. A gate level simulation is one method for reducing errors in a chip design. However, gate level simulations of large designs are extremely expensive. A high level \"black box\" or functional simulation gains in efficiency, yet loses accuracy. It is possible to minimize the individual disadvantages of these two approaches with a hierarchical simulator that permits a mixture of the two levels. Further improvement can be realized by incorporating a dual mode (fixed event list/event-driven) scheduler within this hierarchical simulation environment to control more efficiently the model evaluation sequence. This paper describes such a scheduler, and the user interfaces for it.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Logic Verification System for Very Large Computers Using LSI's 基于大规模集成电路的超大型计算机逻辑验证系统
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600138
Yasuhiro Ohno, Masayuki Miyoshi, Katsuya Sato
{"title":"Logic Verification System for Very Large Computers Using LSI's","authors":"Yasuhiro Ohno, Masayuki Miyoshi, Katsuya Sato","doi":"10.1109/DAC.1979.1600138","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600138","url":null,"abstract":"To aid design verification of very large computers using many LSI's, software tools including a logic simulator with capability of 750,000 gates have been developed.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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