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Eighth IEEE International High-Level Design Validation and Test Workshop最新文献

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Piparazzi: a test program generator for micro-architecture flow verification Piparazzi:微架构流程验证的测试程序生成器
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252470
Allon Adir, E. Bin, Ofer Peled, A. Ziv
{"title":"Piparazzi: a test program generator for micro-architecture flow verification","authors":"Allon Adir, E. Bin, Ofer Peled, A. Ziv","doi":"10.1109/HLDVT.2003.1252470","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252470","url":null,"abstract":"Because of their complexity, modern microprocessors need new tools that generate tests for micro-architectural events. Piparazzi is a test generator, developed at IBM, that generates (architectural) test programs for microarchitectural events. Piparazzi uses a declarative model of the micro-architecture and the user's definition of the required event to create an instance of a Constraint Satisfaction Problem (CSP). It then uses a dedicated CSP solver to generate a test program that covers the specific event. We show how Piparazzi yields significant improvements in covering micro-architectural events, by describing its technology and by exhibiting experimental results. Piparazzi has already been successful in finding both functional and performance bugs that could only be discovered using an exact micro-architectural model of the processor.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133972260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Automatic functional verification of memory oriented global source code transformations 面向内存的全局源代码转换的自动功能验证
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252471
K. Shashidhar, M. Bruynooghe, F. Catthoor, Gerda Janssens
{"title":"Automatic functional verification of memory oriented global source code transformations","authors":"K. Shashidhar, M. Bruynooghe, F. Catthoor, Gerda Janssens","doi":"10.1109/HLDVT.2003.1252471","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252471","url":null,"abstract":"In this paper, we present a fully automatic technique to verify an important class of optimizing program transformations applied to reduce accesses to the data memory. These are prevalent while developing software for power and performance-efficient embedded multimedia systems. The verification of the transformations relies on an automatic proof of functional equivalence of the initial and the transformed program functions. It is based on extracting and reasoning on the polyhedral models representing the dependencies between the elements of the output and the input variables, which are preserved under the transformations considered. If the verification reports failure, the technique also identifies the errors and their location in the function, hence providing an effective means to debug the transformed program function.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131188431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A comparison of BDDs, BMC, and sequential SAT for model checking bdd、BMC和用于模型检查的顺序SAT的比较
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252490
G. Parthasarathy, Madhu K. Iyer, K. Cheng, Li-C. Wang
{"title":"A comparison of BDDs, BMC, and sequential SAT for model checking","authors":"G. Parthasarathy, Madhu K. Iyer, K. Cheng, Li-C. Wang","doi":"10.1109/HLDVT.2003.1252490","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252490","url":null,"abstract":"BDD-based model checking and bounded model checking (BMC) are the main techniques currently used in formal verification. In general, there are robustness issues in SAT-based versus BDD-based model checking. The research reported in this paper attempts to analyze the asymptotic run-time behavior of modern BDD-based and SAT based techniques for model checking to determine the circuit characteristics which lead to worst-case behavior in these approaches. We show evidence for a run-time characterization based on sequential correlation and clause density. We demonstrate that it is possible to predict the worst-case behavior of BMC based on these characterizations. This leads to some interesting insights into the behavior of these techniques on a variety of example circuits.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121127260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG? 遗传算法:点金石还是TPG高层的有效解决方案?
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252491
A. Fin, F. Fummi
{"title":"Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?","authors":"A. Fin, F. Fummi","doi":"10.1109/HLDVT.2003.1252491","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252491","url":null,"abstract":"The paper examines the potentialities of genetic algorithms (GAs) with respect to the development of high-level TPGs. It summarizes at first the most relevant test pattern generation techniques based on genetic algorithms (GAs). This analysis distinguishes the considered techniques with respect to the abstraction level of the design under test. In particular, the effectiveness of gate-level GA-based TPGs is compared with the effectiveness of high-level GA-based TPGs. Differences are deeply investigated. They mainly concern the way genetic operators exploit specific simulation information to heuristically guide the genetic evolution. Moreover, a functional testing framework is described and used to actually measure on high-level descriptions the effectiveness of sophisticated GA-based TPGs in comparison to random approaches. Results are reported on a variety of benchmarks.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125223979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification 基于覆盖导向验证类别仿真的贝叶斯网络与数据挖掘的比较
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252480
Markus Braun, W. Rosenstiel, Klaus-Dieter Schubert
{"title":"Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification","authors":"Markus Braun, W. Rosenstiel, Klaus-Dieter Schubert","doi":"10.1109/HLDVT.2003.1252480","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252480","url":null,"abstract":"Today directed random simulation is one of the most commonly used verification techniques. Because this technique in no proof of correctness, it is important to test the design as complete as possible. But this is a hard to reach goal, that needs a lot of computing power and much human interaction. There has been a proposal for using Bayesian networks to implement an automatic feedback loop (Shai Fine et al, 40th Design Automation Conference, 2003). In addition, this paper introduces another implementation of an automatic feedback loop using data mining techniques. Both approaches are applied to the same design and the results are compared.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
High-level optimization of pipeline design 管道设计的高层次优化
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252473
Jennifer Campbell, N. Day
{"title":"High-level optimization of pipeline design","authors":"Jennifer Campbell, N. Day","doi":"10.1109/HLDVT.2003.1252473","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252473","url":null,"abstract":"We describe an automatic method for synthesizing pipelined processors that optimizes throughput and automatically resolves control and data hazards. We present rules that describe how to resolve hazards based on the data dependencies between functional units. We demonstrate our method by showing optimal pipeline configurations of the DLX.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114444196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mathematical framework for representing discrete functions as word-level polynomials 用字级多项式表示离散函数的数学框架
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252487
D. Pradhan, S. Askar, M. Ciesielski
{"title":"Mathematical framework for representing discrete functions as word-level polynomials","authors":"D. Pradhan, S. Askar, M. Ciesielski","doi":"10.1109/HLDVT.2003.1252487","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252487","url":null,"abstract":"This paper presents a mathematical framework for modeling arithmetic operators and other RTL design modules as discrete word-level functions and proposes a polynomial representation of those functions. The proposed representation attempts to bridge the gap between bit-level BDD representations and word-level representations, such as *BMDs and TEDs.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Testing ThumbPod: Softcore bugs are hard to find 测试ThumbPod:软核bug很难发现
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252478
P. Schaumont, K. Sakiyama, Yi Fan, D. Hwang, Shenglin Yang, A. Hodjat, B. Lai, I. Verbauwhede
{"title":"Testing ThumbPod: Softcore bugs are hard to find","authors":"P. Schaumont, K. Sakiyama, Yi Fan, D. Hwang, Shenglin Yang, A. Hodjat, B. Lai, I. Verbauwhede","doi":"10.1109/HLDVT.2003.1252478","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252478","url":null,"abstract":"We present the debug and test strategies used in the ThumbPod system for Embedded Fingerprint Authentication. ThumbPod uses multiple levels of programming (Java, C and hardware) with a hierarchy of programmable architectures (KVM on top of a SPARC core on top of an FPGA). The ThumbPod project teamed up seven graduate students in the concurrent development and verification of all these programming layers. We pay special attention to the strengths and weaknesses of our bottom-up testing approach.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131994829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrating CNF and BDD based SAT solvers 集成基于CNF和BDD的SAT求解器
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252474
S. Gopalakrishnan, V. Durairaj, P. Kalla
{"title":"Integrating CNF and BDD based SAT solvers","authors":"S. Gopalakrishnan, V. Durairaj, P. Kalla","doi":"10.1109/HLDVT.2003.1252474","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252474","url":null,"abstract":"This paper presents an integrated infrastructure of CNF and BDD based tools to solve the Boolean Satisfiability problem. We use both CNF and BDDs not only as a means of representation, but also to efficiently analyze, prune and guide the search. We describe a method to successfully re-orient the decision making strategies of contemporary CNF tools in a manner that enables an efficient integration with BDDs. Keeping in mind that BDDs suffer from memory explosion problems, we describe learning-based search space pruning techniques that augment the already employed conflict analysis procedures of CNF tools. Our infrastructure is targeted towards solving those hard-to-solve instances where contemporary CNF tools invest significant search times. Experiments conducted over a wide range of benchmarks demonstrate the promise of our approach.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131198182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Verifying LOC based functional and performance constraints 验证基于功能和性能约束的LOC
Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252479
X. Chen, H. Hsieh, F. Balarin, Yosinori Watanabe
{"title":"Verifying LOC based functional and performance constraints","authors":"X. Chen, H. Hsieh, F. Balarin, Yosinori Watanabe","doi":"10.1109/HLDVT.2003.1252479","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252479","url":null,"abstract":"In the era of billion-transistor design, it is critical to establish effective verification methodologies from the system level all the way down to the implementations. Assertion languages (e.g. IBM's Sugar2.0, Synopsys's OpenVera) have gained wide acceptance for specifying functional properties for automatic validation. They are, however, based on linear temporal logic (LTL), and hence have certain limitations. Logic of constraints (LOC) was introduced for specifying quantitative performance constraints, and is particularly suitable for automatic transaction level analysis. We analyze LTL and LOC, and show that they have different domains of expressiveness. Using both LTL and LOC can make the verification process more effective in the context of simulation assertion checking as well as formal verification. Through industrial case studies, we demonstrate the usefulness of this verification methodology.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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