Eighth IEEE International High-Level Design Validation and Test Workshop最新文献_第3页

Relating vehicle-level and network-level reliability through high-level fault injection 通过高级故障注入将车辆级和网络级可靠性联系起来

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252477

Fulvio Corno, P. Gabrielli, S. Tosato

引用次数: 3

Nano, quantum, and molecular computing: are we ready for the validation and test challenges? 纳米、量子和分子计算:我们准备好迎接验证和测试挑战了吗?

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252467

S. Shukla, R. Karri, S. Goldstein, F. Brewer, K. Banerjee, S. Basu

{"title":"Nano, quantum, and molecular computing: are we ready for the validation and test challenges?","authors":"S. Shukla, R. Karri, S. Goldstein, F. Brewer, K. Banerjee, S. Basu","doi":"10.1109/HLDVT.2003.1252467","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252467","url":null,"abstract":"In the recent years a lot of research effort is being spent in the areas of nanotechnology, quantum computation, and biologically inspired computing. As we are faced with various challenges regarding their implementability, architectural visions, and design automation, not much has been done in the field of high level design and validation in looking further into the future, and ponder about the state of the art in design validation and test in such miniscule technology era. Very few reported research work have surfaced on the design and validation challenges for these technologies. However, this certainly is a matter of concern because the technology of the small will be ridden with random faults and hence architectural design strategies need to change to take into account these stochastic models of failures to build robust designs. Validation of such designs also have to capture the stochastic behavioral models of the technology, and hence traditional validation and testing techniques will not work directly. Are we getting ready with our theory; technology and tools to address these challenges? This futuristic panel asks technology and computer aided design experts, as well as finding agency program managers questions about the technological barriers to be surpassed, as well as how the funding agencies such as NSF are ramping up for this technological future.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130963982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

High-level test generation for hardware testing and software validation 为硬件测试和软件验证生成高级测试

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252488

O. Goloubeva, M. Reorda, M. Violante

引用次数: 8

Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking 在不关心和冗余序列元素存在的情况下进行匹配，以进行序列等价性检查

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252486

S. Rahim, B. Rouzeyre, L. Torres, J. Rampon

{"title":"Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking","authors":"S. Rahim, B. Rouzeyre, L. Torres, J. Rampon","doi":"10.1109/HLDVT.2003.1252486","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252486","url":null,"abstract":"Full sequential equivalence checking by state space traversal has been shown to be unpractical for large designs. To address state space explosion new approaches have been proposed that exploit structural characteristics of a design and make use of multiple analysis engines (e.g. BDDs, Simulation, SAT) to transform the sequential equivalence checking problem into a combinational equivalence checking problem. While these approaches, based on induction techniques, have been successful in general, they are not able to reach proof of equivalence in presence of complex transformations between the reference design and its implementation. One of these transformations is redundant Flip-Flops (FFs) removal. FFs may be removed by redundancy removal, or don't care optimization techniques applied by synthesis tools. Consequently, some FFs in the reference design may have no equivalent FFs in the implementation net-list. Latest researches in this area have proposed specific solutions for particular cases. Matching in the presence of redundant constant input FFs has been addressed and identification of sequential redundancy is performed. This paper presents an indepth study of some possible causes of unmatched FFs due to redundancy removal, and proposes a generic approach to achieve prove of equivalence in presence of redundant FFs. Our approach is independent from specific synthesis transformations. It is able to achieve matching in presence of complex redundancies, and is able to perform formal equivalence checking in presence of don't cares. The experimental results show a significant improvement in the matching rates of FFs when compared to industrial equivalence checking tools. This higher matching is directly translated to a higher success rate in proving equivalency.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134257911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A method for the evaluation of behavioral fault models 行为错误模型的评估方法

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252492

Emilio Gaudette, M. Moussa, I. Harris

引用次数: 7

Enhancing SAT-based equivalence checking with static logic implications 通过静态逻辑含义增强基于sat的等价性检查

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252476

Rajat Arora, M. Hsiao

引用次数: 15

ATPG-based preimage computation: efficient search space pruning with ZBDD 基于atpg的原图像计算:基于ZBDD的高效搜索空间剪枝

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-07-28 DOI: 10.1109/HLDVT.2003.1252484

Kameshwar Chandrasekar, M. Hsiao

引用次数: 9