Enhancing SAT-based equivalence checking with static logic implications

Rajat Arora, M. Hsiao
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引用次数: 15

Abstract

We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC) by statically adding meaningful clauses to the CNF formula of the miter circuit. A fast preprocessing quickly builds up the implication graph for the miter circuit under verification, resulting in a large set of direct, indirect and extended backward implications. The non-trivial implications are converted into two-literal clauses and added to the miter CNF database. These added clauses constrain the search space, and provide correlation among the different variables, which enhances the Boolean Constraint Propagation (BCP). Experimental results on ISCAS'85 CEC instances show that with the added clauses, an average speedup of more than 950x was achieved.
通过静态逻辑含义增强基于sat的等价性检查
本文提出了一种改进基于sat的组合等效检验(CEC)的新方法,即在斜接电路的CNF公式中静态地添加有意义的子句。通过快速的预处理,快速建立了待验证的斜接电路的隐含图,从而产生了大量的直接、间接和扩展的向后隐含。重要的含义被转换成双文字子句,并添加到miter CNF数据库中。这些增加的子句约束了搜索空间,并提供了不同变量之间的相关性,增强了布尔约束传播(BCP)。在ISCAS’85 CEC实例上的实验结果表明,增加了子句后,平均速度提高了950x以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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