Eighth IEEE International High-Level Design Validation and Test Workshop最新文献

What's the next 'big thing' in simulation-based verification? 基于仿真的验证的下一个“大事件”是什么?

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252493

M. Levinger, A. Ziv, B. Bailey, J. Abraham, B. Bentley, W. Joyner, Yaron Kas

引用次数: 1

Functional vector generation for assertion-based verification at behavioral level using interval analysis 使用区间分析在行为层面生成基于断言的验证功能向量

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252482

Í. Ugarte, P. Sánchez

{"title":"Functional vector generation for assertion-based verification at behavioral level using interval analysis","authors":"Í. Ugarte, P. Sánchez","doi":"10.1109/HLDVT.2003.1252482","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252482","url":null,"abstract":"The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts that it is unlikely that verification will be manageable for designs envisioned beyond 2007 without design-for-verifiability. Some CAD vendors have promoted assertion-based verification (ABV) as one of the first commercial design-for-verification techniques. In order to handle complex design, this methodology has to be complemented with tools that automatically generate vectors or counterexamples that violate/verify proposed assertions or constraints. This paper presents an assertion checking technique for behavioral models that combines a non-linear solver and state exploration techniques and avoids expanding behavior into logic equations. The kernel of the technique is a modified interval analysis (MODIA) that avoids most of the problems of classical interval analysis (IA) and improves reuse during vector generation. The results show that the proposed technique is able to handle very efficiently data-dominated designs, which research and commercial assertion/property checkers are unable or need more CPU effort to verify.","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Enhancing the control and efficiency of the covering process [logic verification] 加强覆盖过程的控制和效率[逻辑验证]

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252481

S. Fine, A. Ziv

引用次数: 10

Refactoring digital hardware designs with assertion libraries 用断言库重构数字硬件设计

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252472

F. M. D. Paula, C. Coelho, H. Foster, J. Nacif, Joseph Tompkins, A. O. Fernandes, D. Silva

引用次数: 1

Scheduling of transactions for system-level test-case generation 系统级测试用例生成的事务调度

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252489

Roy Emek, Y. Naveh

引用次数: 9

FPgen - a test generation framework for datapath floating-point verification 用于数据路径浮点验证的测试生成框架

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252469

M. Aharoni, Sigal Asaf, L. Fournier, A. Koyfman, Raviv Nagel

引用次数: 47

Software-based self-test methodology for crosstalk faults in processors 基于软件的处理器串扰故障自检方法

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252468

Xiaoliang Bai, Li Chen, S. Dey

{"title":"Software-based self-test methodology for crosstalk faults in processors","authors":"Xiaoliang Bai, Li Chen, S. Dey","doi":"10.1109/HLDVT.2003.1252468","DOIUrl":"https://doi.org/10.1109/HLDVT.2003.1252468","url":null,"abstract":"Due to signal integrity problems inherent sensitivity to timing, power supply voltage and temperature, it is desirable to test AC failures such as crosstalk-induced errors at operational speed and in the circuit's natural operational environment. To overcome the daunting cost and increasing performance hindrance of high-speed external testers, Software-Based. Self-Test (SBST) is proposed as a high-quality. low-cost at-speed testing solution for AC failures in programmable processors and System-on-Chips (SoC). SBST utilizes low-cost testers, applies tests and captures test responses in the natural operational environment. Hence SBST avoids artificial testing environment and external tester induced inaccuracies. Different from testing for stuck-at faults, testing for crosstalk faults requires a sequence of test vectors delivered at the operational speed. SBST applies tests in functional mode using instructions. Different instructions impose different controllability and observability constraints on a module-under-test (MUT). The complexity of searching for an appropriate sequence of instructions and operands becomes prohibitively high. In this paper, we propose a novel methodology to conquer the complexity challenge by efficiently combining structural test generation technique with instruction-level constraints. MUT in several time frames is automatically flattened and augmented with Super Virtual Constraint Circuits (SuperVCCs), which guide an automatic test pattern generation (ATPG) tool to select. appropriate test instructions and operands. The proposed methodology enables automatic test-program generation and high-fidelity test solution:for AC failures. Experimental results are shown on a commercial embedded processor (Xtensa/sup /spl trade// from Tensilica Inc).","PeriodicalId":344813,"journal":{"name":"Eighth IEEE International High-Level Design Validation and Test Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Logic transformation and coding theory-based frameworks for Boolean satisfiability 基于逻辑变换和编码理论的布尔可满足性框架

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252475

D. Pradhan

引用次数: 4

BDD-based verification of scalable designs 基于bdd的可扩展设计验证

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252485

Daniel Große, R. Drechsler

引用次数: 3

Redundant functional faults reduction by saboteurs synthesis [logic verification] 破坏者合成减少冗余功能故障[逻辑验证]

Eighth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2003-11-12 DOI: 10.1109/HLDVT.2003.1252483

F. Fummi, C. Marconcini, G. Pravadelli

引用次数: 5