1994 Proceedings. 44th Electronic Components and Technology Conference最新文献_第8页

Cracking failures in lead-on-chip packages induced by chip backside contamination 芯片背面污染导致的片上铅封装开裂失效

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367634

M. Aamagi, H. Seno, K. Ebe, R. Baumann, H. Kitagawa

{"title":"Cracking failures in lead-on-chip packages induced by chip backside contamination","authors":"M. Aamagi, H. Seno, K. Ebe, R. Baumann, H. Kitagawa","doi":"10.1109/ECTC.1994.367634","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367634","url":null,"abstract":"The increasingly severe demands of concurrently increasing die size while reducing package size have made the mechanical stability of novel surface mount technologies a primary concern. Package cracks induced by interfacial delamination between the chip backside surface and the epoxy molding resin are a major failure mode in Lead-On-Chip (LOC) packages. This interfacial delamination is caused by contamination of the backside surface by the wafer tape adhesive. The physical and chemical parameters of the backside surface and tape adhesive which lead to interfacial delaminations in LOC packages are described along with a method to alleviate the problem. To investigate which adhesive attributes impacted interfacial delamination, wafer tape adhesive samples were prepared with a variety of different base polymers, oligomers, cross-linking agents, initiative agents, and additive agents. The degree and type of backside contamination left by these various adhesives was determined with scanning electron microscope (SEM) and scanning acoustic tomography (SAT) techniques. The adhesive and the chip backside surfaces were characterised with viscoelastic, particle count, water contact angle, and atomic force microscope (AFM) measurements.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Impact of moisture/reflow induced delaminations on integrated circuit thermal performance 湿气/回流诱导分层对集成电路热性能的影响

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367543

T. R. Conrad, R. L. Shook

{"title":"Impact of moisture/reflow induced delaminations on integrated circuit thermal performance","authors":"T. R. Conrad, R. L. Shook","doi":"10.1109/ECTC.1994.367543","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367543","url":null,"abstract":"Ambient moisture uptake in plastic surface mount IC packages can cause delamination of critical internal surfaces within the package during reflow assembly. Delaminations can result in reduced thermal cycling life performance or provide for a pathway for the ingress of chemicals and contaminates. The effects that moisture/reflow induced delaminations can have on the thermal performance of plastic packaged ICs are not entirely understood. In this paper, the thermal performance of moisture/reflow delaminated ICs is reported. The effective sensitivity of the thermal performance as a result of the moisture/reflow induced delaminations was measured by experimental thermal resistance measurements (/spl theta//sub JA/) and compared to theoretical calculations based on Finite Element Analysis (FEA). Both 3-D and 2-D FEA models were developed for predictive responses which gave excellent correlation to the experimental measurements. The results showed that interfacial delaminations can cause a measurable increase in /spl theta//sub JA/. The magnitude of the increase is found to be proportional to the power consumption of the device and dependent on the delamination gap thickness. Expected reliability degradation as a result of die temperature rise from the interfacial delaminations is most significant for plastic packaged devices of power ratings greater than about 1 W.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130563696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Development of 0.45 mm thick Ultra-Thin Small Outline Package (UTSOP) 0.45 mm厚超薄小轮廓封装(UTSOP)的研制

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367547

S. Omi, T. Maruyama, T. Ishio, A. Narai, Y. Sota, K. Toyosawa, K. Fujiita, T. Maeda

引用次数: 3

Iterative direct solution method for thermal analysis of electronic equipment 电子设备热分析的迭代直接解法

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367603

M. Reill

{"title":"Iterative direct solution method for thermal analysis of electronic equipment","authors":"M. Reill","doi":"10.1109/ECTC.1994.367603","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367603","url":null,"abstract":"The numerical procedure described in this work performs analysis of 3-dimensional structures by partitioning the geometry in basic blocks, which can be described as multi-layer-structures with rectangular base area. Combining such basic regions, complex geometries like stacked structures can be treated. The Laplacian equation describing the steady state heat flux is solved efficiently in three dimensions using a Fast Fourier Transform (FFT) algorithm. By the use of an iterative procedure handling of inhomogeneous, nonlinear boundary conditions on the top and bottom side of the geometry and modeling complex geometries by matching the solution at the interface of two or more basic blocks is possible. This allows to take into account boundary conditions calculated by the analytical solution of the Navier-Stokes equations describing convection and the Stefan Boltzmann law describing radiation. Experimental studies using infrared thermography, thermal sensors and laser doppler velocimetry were carried out. By measurement of the temperature distribution and the flow field it is shown, that the simultaneous solution of the heat flux in the solid structure and the heat-transfer by boundary approximation improves the accuracy of temperature computation and expands the application range of the Fourier method. It is shown, that parallel placed substrates with bare chips can be handled with high accuracy by the proposed model for laminar flow. The model gives good results for mountings up to 0.6 mm height. For low fluid velocities up to 1 m/s and natural convection the model works also for higher mountings (e.g. SMD). Further applications demonstrate the accuracy and applicability of the presented program. The simple model-creation and the numerical efficiency enables the handling of problems with a high number of components and high aspect ratios between the components and the board. Analytical models describing heat dissipation in special applications can be easily incorporated for simultaneous solution.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The importance of material selection for flip chip on board assemblies 倒装芯片板上组件材料选择的重要性

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367560

G. O'malley, J. Giesler, S. Machuga

{"title":"The importance of material selection for flip chip on board assemblies","authors":"G. O'malley, J. Giesler, S. Machuga","doi":"10.1109/ECTC.1994.367560","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367560","url":null,"abstract":"Flip chip technology, where the unpackaged silicon chip is assembled directly to an organic substrate, provides an unique interconnect structure that significantly reduces the substrate area required by traditional surface mount integrated circuit packages. Without the protection for the chip that a package body affords however, reduced mechanical robustness and a decrease in reliability performance are potential concerns. In addition, the inherent thermal mismatch between the chip and substrate, particularly with an organic printed circuit board, will produce an accumulation of stress in the solder joints under normal operating conditions that can result in relatively premature failures. Coupling the chip and substrate together with an encapsulation material under the chip face has successfully overcome these mechanical and reliability issues. However, the success of the encapsulation is dependent on many factors. Among these are the encapsulant's material properties, and its compatibility with the chip and substrate surfaces. Thus, the selection of the basic materials to be used in the Flip Chip on Board (FCOB) assembly are interrelated and critical to the subsequent performance of the completed assembly.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130109369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Memory package with LOC structure using new adhesive material 采用新型粘接材料的LOC结构内存封装

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367535

H. Nakayoshi, N. Izawa, T. Ishikawa, T. Suzuki

{"title":"Memory package with LOC structure using new adhesive material","authors":"H. Nakayoshi, N. Izawa, T. Ishikawa, T. Suzuki","doi":"10.1109/ECTC.1994.367535","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367535","url":null,"abstract":"The LOC (Lead On Chip) structure has been considered as an effective technology to encapsulate a large LSI memory chip into a small package. The main feature of the structure is contact of leadframes onto the active chip area with adhesive sandwiched in between. Therefore, the design concept of LOC greatly depends on the characteristics of the adhesive layer. The key technologies for LOC development are summarized as: 1. To lessen damage on chip during die-attach and wire bonding; 2. To secure sufficient wire bendability above the organic adhesive; and 3. To reduce package crack rate during the solder reflowing process. We have developed a new adhesive tape which is composed of single-layer thermoplastic polyimide siloxanes. Due to the absence of a base film, the single layer adhesive can be fabricated to any desirable thickness. During its softening process, the thick adhesive film encloses dust that, otherwise, could damage the chip surface. These properties, by providing a large Young's modulus of the film at high temperature and contamination-free lead surface, enable us to secure sufficient lead-wire bendability. The other materialistic advantage of the adhesive is its low moisture absorption. The low moisture absorption results in high resistance against package crack caused by the solder reflowing process. In this paper, we describe how we have selected the LOC adhesive tape through the evaluations of the assembly process and have successfully developed a highly productive and reliable memory package with LOC structure.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129480437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Membrane based actuator-integrated force arrays 基于薄膜的致动器-集成力阵列

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367530

J. Bousaba, S. Bobbio, S. Goodwin-Johansson, M. Kellam, B. Dudley, J. Jacobson, S. Jones, T. D. DuBois, F. Tranjan

引用次数: 1

Carrier and socket technology for high pin count QFP packages 用于高引脚数QFP封装的载波和插座技术

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/95.370747

J. Foerstel

引用次数: 2

Packaging of high reliability couplers 高可靠性耦合器的封装

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367505

D.R. Young, A. Morrow, K. Gadkaree, D. E. Quinn

引用次数: 1

Liquid encapsulant and uniaxial calibration mechanical stress measurement with the ATC04 assembly test chip 用ATC04组装测试芯片进行液体封装和单轴校准机械应力测量

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367586

J. Sweet, D. Peterson, J. Emerson

引用次数: 19