2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献_第6页

A 600-V GaN Active Gate Driver with Level Shifter Common-Mode Noise Sensing for Built-in dV/dt Self-Adaptive Control 一种内置dV/dt自适应控制的600 v GaN有源栅极驱动器，带电平移位共模噪声检测

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147641

Tianqi Liu, R. Martins, Yan Lu

{"title":"A 600-V GaN Active Gate Driver with Level Shifter Common-Mode Noise Sensing for Built-in dV/dt Self-Adaptive Control","authors":"Tianqi Liu, R. Martins, Yan Lu","doi":"10.1109/ISPSD57135.2023.10147641","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147641","url":null,"abstract":"This paper proposes a 600- V half-bridge GaN active gate driver with built-in dV/dt self-adaptive control utilizing a common-mode (CM) noise sensing and amplifying unit. The two 600- V LDMOS FETs existing in the conventional level shifter are used to sense the CM noises. When the dV/ dt rate is large enough, the sensed CM noises will be amplified and then rapidly provide a pull-down gate current for reducing the turn-on speed. As the dV/dt rate becomes smaller, the pull-down gate current will decrease adaptively, which achieving double peaks in the waveform of driving current. Compared to adding an extra high-voltage capacitor or LDMOS as a dV/dt sensor, this method has no additional area overhead and negligible control delay. At the same slew rate, we compare the low-side gate noises induced by Miller coupling at condition of either only $R_{ON}$ or the proposed self-adaptive adjustments. It shows that the noise peak in $V_{GL}$ for self-adaptive control decreases 46% at $V_{JN}=300mathrm{V}$ and also the noise envelope becomes smaller due to the dV/dt adjustment, dramatically reducing the probability of shoot-through current in the half bridge.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121624023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

First Demonstration of 600 V 4H-SiC Lateral Bi-Directional Metal-Oxide-Semiconductor Field-Effect Transistor (LBiDMOS) 600 V 4H-SiC横向双向金属氧化物半导体场效应晶体管(LBiDMOS)首次演示

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147546

S. Jang, S. Isukapati, Dongyoung Kim, Woongje Sung

引用次数: 0

Strain Engineering in Modern Si Trench Power MOSFETs — A Performance Booster for Future Generations 现代硅沟槽功率mosfet的应变工程-未来一代的性能助推器

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147538

Stefan Karner, O. Blank, J. Keckes, M. Rösch, Seung Hwan Lee, S. Léomant

{"title":"Strain Engineering in Modern Si Trench Power MOSFETs — A Performance Booster for Future Generations","authors":"Stefan Karner, O. Blank, J. Keckes, M. Rösch, Seung Hwan Lee, S. Léomant","doi":"10.1109/ISPSD57135.2023.10147538","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147538","url":null,"abstract":"The ongoing trend towards electrification and digitalization requires the continuous improvement of high frequency, high power density switching solutions such as split-gate Si trench power MOSFETs. However, their pure figure of merit (FOM) related performance improvement through conventional scaling has reached a physical limit. Similar to the approaches for planar MOSFETs, the device performance can also be improved by strain engineering, leading to a modified charge carrier mobility in the electrically active monocrystalline Si. Therefore, a novel strain engineering approach is proposed for Si trench power MOSFETs, adding a strain functionality to the trenches on top of their charge compensation purpose. It is shown that the device performance is increased by up to 16.8%, which is achieved by not only altering the mobility in the channel but also influencing the drift region of the device. Since the correlation of electrical and mechanical device characteristics is key to effectively implement strain engineering concepts in Si trench power MOSFETs, high-precision nanoscale stress and strain characterization techniques as well as finite element mechanical simulations are established and presented.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power Cycling of Sintered SiC Power MOSFET Baseplate-less Modules with Aluminum Oxide and Silicon Nitride Substrates 氧化铝和氮化硅衬底烧结SiC功率MOSFET无基板模块的功率循环

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147471

Ivana Kovacevic-Badstuebner, E. Mengotti, P. Natzke, S. Race, E. Bianda, J. Jormanainen, U. Grossner

引用次数: 0

Application of a Smart Gate Driver to Detect Aging in SiC Power MOSFETs 智能栅极驱动器在SiC功率mosfet老化检测中的应用

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147513

Mengqi Wang, Jiupeng Zhang, W. Ng, H. Nishio, Motomitsu Iwamoto, H. Sumida

{"title":"Application of a Smart Gate Driver to Detect Aging in SiC Power MOSFETs","authors":"Mengqi Wang, Jiupeng Zhang, W. Ng, H. Nishio, Motomitsu Iwamoto, H. Sumida","doi":"10.1109/ISPSD57135.2023.10147513","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147513","url":null,"abstract":"In this paper we present an integrated smart gate driver (SGD) capable of in-operation detection of SiC power MOSFET aging. The SGD IC monitors the discrete time differentiated (DTD) gate voltage slope, $Delta V_{GS}$, to identify the time to start of the Miller plateau, $t_{1}$, during turn-on. Under known operating conditions, the value of $t_{1}$ can be used as an aging indicator to detect changes in the Miller plateau due to threshold voltage shifts. A synthesized digital central control unit (CCU) within the SGD can adjust the gate drive profile and gate drive bus voltage ($V_{DR}$) based on the aging-induced changes in $t_{1}$. We demonstrate that following 200 hours of high-temperature gate bias (HTGB) at 200 °C, $V_{DR, stress}=30 mathrm{V}$, aging-induced gate degradation of a 1.2 kV 75A SiC MOSFET results in a decrease in drain current ($I_{D}$) by 1.5%. An increase in $V_{text{MP}}$ by 0.5 V can restore $I_{D}$ by 1.7% to pre-aged levels. This is achieved by adjusting the digital pulse width modulation (PWM) duty cycle of the on-chip DC-DC boost converter.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129596613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Characterization and Analysis of 4H-SiC Lateral MOSFET (LMOS) for High-Voltage Power Integrated Circuits 用于高压电源集成电路的4H-SiC横向MOSFET (LMOS)的电学特性与分析

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147418

Li Liu, Jue Wang, Zishi Wang, Miaoguang Bai, Junze Li, Zhengyun Zhu, Hongyi Xu, Na Ren, Qing Guo, Kuang Sheng

引用次数: 0

Investigation of BVdss instability in trench power MOSFET through DLTS, electrical characterization and TCAD simulations 通过DLTS、电学表征和TCAD仿真研究沟槽功率MOSFET中BVdss的不稳定性

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147489

Marina Ruggeri, P. Calenzo, F. Morancho, L. Masoero, R. Germana, Alessandro Nodari, R. Monflier

引用次数: 0

Exploitation of Hole Injection and Spreading for Dynamic Enhancement in p-GaN Gate HEMT under Room/High Temperatures 室温/高温下p-GaN栅极HEMT动态增强的空穴注入和扩散研究

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147649

Junjie Yang, Yanlin Wu, Muqin Nuo, Zheng-wei Chen, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei

{"title":"Exploitation of Hole Injection and Spreading for Dynamic Enhancement in p-GaN Gate HEMT under Room/High Temperatures","authors":"Junjie Yang, Yanlin Wu, Muqin Nuo, Zheng-wei Chen, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei","doi":"10.1109/ISPSD57135.2023.10147649","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147649","url":null,"abstract":"In this study, we investigate the role of hole injection and spreading in a p-GaN gate HEMT for addressing buffer-related dynamic $R_{text{ON}}$ degradations. The proposed structure includes a buried AlGaN layer that acts as a hole barrier and provides a hole spreading channel (BHSC) under the 2DEG channel. During the on-state, holes are injected from the gate and spread along the BHSC. We observe that the hole injection is enhanced with increasing temperatures. The lateral spreading of holes is critical for suppressing buffer trapping outside of the gate region. As the suppression of buffer trapping is enhanced with an increase in $V_{text{GS}}$, the dynamic $R_{text{ON}}$ is dramatically reduced. We then adopt the widely used back-gating test to evaluate the dynamic $R_{text{ON}}$ when buffer trapping is intentionally introduced. Finally, we demonstrate that the proposed device with BHSC exhibits nearly zero buffer-related dynamic $R_{text{ON}}$ degradation from room temperature to 125°C.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"42 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simplified Open-Loop Transfer Functions to Analyze Influential Parasitic Parameters for Oscillation Caused by Parallel Connected Transistors 简化开环传递函数分析并联晶体管振荡寄生参数的影响

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147582

Hiroto Sakai, Yuta Okawauchi, Shinji Yato, Hideo Araki, Takayuki Atago, K. Nakahara

引用次数: 0

Package Design Consideration for Suppressing Radiated EMI Noise in Semi-Bridgeless PFC Converters 抑制半无桥PFC变换器辐射EMI噪声的封装设计考虑

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147635

Satoshi Yoshida, T. Yasuzumi, Tsuguhiro Tanaka, Yasuyuki Fujiwara

引用次数: 1