2018 IEEE Electron Devices Kolkata Conference (EDKCON)最新文献_第8页

Multiple Quantum Well IMPATT Sources based on Si~3C-SiC Heterostructures Operating at Millimeter-Wave and Terahertz Frequency Bands 基于Si~3C-SiC异质结构的毫米波和太赫兹频段多重量子阱冲击源

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770499

M. Ghosh, A. Acharyya

引用次数: 1

Simulation based Performance Analysis of a Double Gate Work Function Engineered Doped Tunnel FET 基于仿真的双栅功函数掺杂隧道场效应管性能分析

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770435

Supratim Das

引用次数: 0

Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications 势垒厚度变化对栅极工程TM-DG异质结构MOSFET抑制SCE及其SOC应用模拟、射频、线性性能的影响

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770475

Biswajit Baral, S. Biswal, P. Priya, Sarita Pani, S. Swain

引用次数: 0

Energy-Efficient Approximate Squaring Hardware for Error-Resilient Digital Systems 面向容错数字系统的节能近似平方硬件

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770453

Merin Loukrakpam, C. L. Singh, Madhuchhanda Choudhury

引用次数: 3

Impact of Device Parameters on the Threshold Voltage of Double-Gate, Tri-Gate and Gate-All-Around MOSFETs 器件参数对双栅、三栅和栅全能mosfet阈值电压的影响

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770425

Shankaranand Jha, S. K. Choudhary

引用次数: 7

Analysis of Different Gate Dielectric Materials in Carbon Nanotube Field Effect Transistor (CNFET) Using Optimization Technique 碳纳米管场效应晶体管(CNFET)中不同栅极介质材料的优化分析

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770503

Ankit Dixit, N. Gupta

引用次数: 3

Optimization of the Components of a Visible Light Communication System for Efficient Data Transfer 有效数据传输的可见光通信系统组件的优化

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770450

Sujit Chatterjee, B. Tiru

{"title":"Optimization of the Components of a Visible Light Communication System for Efficient Data Transfer","authors":"Sujit Chatterjee, B. Tiru","doi":"10.1109/EDKCON.2018.8770450","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770450","url":null,"abstract":"For efficient data transfer, it is necessary that every component of a communication system be optimized. The same is the case for Visible Light Communication where the components are optoelectronic devices like the light emitting diodes, photodiodes, solar cells and the necessary transmitting and receiving electronics. In this paper, such a system is studied and optimized for efficient data transfer. The experimental arrangement for this is described in detail and the efficiency of the system in terms of distance, maximum bit rate and bit error rate are studied. The variability analyzed are different types of drivers used to drive the light emitting diode and photo detectors namely photodiode and solar cell. It is found that with this experimental arrangement, a 1W LED can be used to transfer data at a rate of more than 1 Mbps through a distance of 30 cm which, though decreases, maintains more than 0.7 Mbps at 475 cm using a photodiode. The maximum bit rate obtained in photodiode is 15.06 and 22.5 times that of a solar cell at a transceiver distance of 30 cm and 225 cm respectively. The distance of significant reception depends on the type of driver and photo detector used. An experimental arrangement is proposed that reduces flicker, both for low and high data rates. The results of the study can be used in future development of a successful system. The setup is also used for online monitoring of the ambient temperature and data transfer between PC's.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127678274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Real-Time Acquisition and Filtering for MEMS-based Accelerometer Data in Microcontroller 基于mems的加速度计数据实时采集与滤波的微控制器设计

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770488

Samruddhi Chikhalikar, Omkar Khandekar, C. Bhattacharya

引用次数: 1

Investigations on Infrared(IR) Sensitive Material for Microbolometer Using Material Selection Approaches 用材料选择方法研究微热计红外敏感材料

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770504

Devanshi Gupta, N. Gupta

引用次数: 0

FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis 基于RNS加法器的三值逻辑域MAC单元信号处理算法的FPGA实现及性能分析

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770463

Aniruddha Ghosh, A. Sinha

{"title":"FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis","authors":"Aniruddha Ghosh, A. Sinha","doi":"10.1109/EDKCON.2018.8770463","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770463","url":null,"abstract":"Digital signal processing (DSP) based applications are designed using various types of DSP algorithms which are computationally intensive. So, DSP-based applications widely utilize Multiply-Accumulate (MA C) operation for accomplishing speed. In contrast with the binary number system, Residue Number Systems (RNS) is considered to be more prominent because of their abilities of carrying out carry-free arithmetic operations like addition, subtraction. Ternary value logic (TVL) offers several advantages like reduced chip area as well as overall delay, over conventional binary number system. Designing superior adder and multiplier have become the major concern for implementing high performance signal processing applications. To improve the performance of MA C unit, a new architecture is proposed in this paper. In this paper, MA C unit is implemented using ternary multiplier and RNS adder in TVL domain. The major bottleneck of TVL to RNS conversion and vice versa has introduced huge complexity which leads to decreased efficiency of performance due to large conversion time. The performance of RNS based system can be enhanced by choosing relative prime moduli set as improper selection of moduli will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2