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2018 IEEE Electron Devices Kolkata Conference (EDKCON)最新文献

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Performance Analysis of CdTe Based PV Array Using Parameter Extraction Techniques 基于参数提取技术的CdTe基光伏阵列性能分析
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770513
Debamita Roy, I. Mal, D. P. Samajdar
{"title":"Performance Analysis of CdTe Based PV Array Using Parameter Extraction Techniques","authors":"Debamita Roy, I. Mal, D. P. Samajdar","doi":"10.1109/EDKCON.2018.8770513","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770513","url":null,"abstract":"Designing of Photovoltaic (PV)modules are essential as it can successfully predict the deliverable output power form the module under variable environmental conditions. The paper presents a detailed step by step modeling of a solar array delivering a maximum output power of 50 kW. Two different parameter estimation techniques are used to extract the unknown parameters in a single diode model of a solar cell. The two sets of unknown parameters are then used to plot the I-V and P-V characteristic curves at STC for a PV Module FS- 4105–2 (CdTe based PV Module). Both the models use different expressions for reverse saturation current and photogenerated current. The effect of the variation of temperature and irradiance on the P-V and I-V has been studied and compared using the two techniques. The analytical modeling and realization of the PV Module is done using MATLAB software.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Strain on Density of States and Directional Dependent Electron Effective Mass of Two Dimensional Intrinsic Graphene 应变对二维本征石墨烯态密度和方向相关电子有效质量的影响
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770512
A. Mondal, Anup Dey, B. Maiti
{"title":"Effect of Strain on Density of States and Directional Dependent Electron Effective Mass of Two Dimensional Intrinsic Graphene","authors":"A. Mondal, Anup Dey, B. Maiti","doi":"10.1109/EDKCON.2018.8770512","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770512","url":null,"abstract":"A simple theoretical model is presented to study the density of states (DOS) and directional dependence of electron effective mass (DD-EEM) of graphene in presence of anisotropic strain field. A generalized expression of anisotropic dispersion relation in tight-binding approximation (TBA) is used to determine DOS and DD-EEM. It is found that both DOS and DD-EEM show nonlinear variation with induced strain and its direction of application. In graphene strain field is highly anisotropic and that infuses nonlinearity in dispersion energy. This is the key to the control of transport properties of graphene by inducing strain in it.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Fabrication of Electro-Thermal 1-D Micro-Mirror 电热一维微镜的设计与制造
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770509
Vikram Maharshi, V. Mere, A. Agarwal
{"title":"Design and Fabrication of Electro-Thermal 1-D Micro-Mirror","authors":"Vikram Maharshi, V. Mere, A. Agarwal","doi":"10.1109/EDKCON.2018.8770509","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770509","url":null,"abstract":"This paper presents design and fabrication of MEMS 1-D micro mirror using thermally actuated bimorph actuator, for out of plane actuation application. Bimorph actuator was made of aluminum and silicon dioxide materials. Micro mirror performance was simulated using COMSOL multiphysics tool. Maximum displacement and temperature profile with voltage along micro mirror were presented. Aluminum was used as heater element as well as top layer of bimorph layer. Micro mirror was successfully released using surface micromachining with copper as sacrificial layer.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Review on the Effects of Technology on CMOS and CPL Logic Style on Performance, Speed and Power Dissipation CMOS和CPL逻辑方式技术对性能、速度和功耗的影响综述
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770506
I. Hussain, Avtar Singh, S. Chaudhury
{"title":"A Review on the Effects of Technology on CMOS and CPL Logic Style on Performance, Speed and Power Dissipation","authors":"I. Hussain, Avtar Singh, S. Chaudhury","doi":"10.1109/EDKCON.2018.8770506","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770506","url":null,"abstract":"With the advancement in CMOS technology, process related limitations, power dissipation, leakage etc. are main challenges for VLSI. So, in the field of VLSI an alternative device technology is the need of the time. Many new next generation devices have come up very recently, especially, the Carbon Nanotubes (CN)Field Effect Transistor (CNTFET)which has many advantages over conventional MOSFETs. MOSFETs like CNTFETs are the best for high-performance VLSI design as it fits well with the traditional MOS-VLSI design. This work presents an inclusive study and analysis of the results of simulation on different logic families. Moreover, the effect of technology nodes on leakage, power and delay are also highlighted in this simulation study. The logic families considered here are the conventional Complementary-Metal-Oxide-Semiconductor (CMOS)and Complementary-Pass-transistor-Logic (CPL)logics along with the CNTFET based logic. Based on these logic styles, NAND, NOR, XOR and multiplexer are implemented. An analysis is carried out to calculate power, worst delay and power delay product (PDP). This work will give the best select of logic style for VLSI applications useful for low power and high speed. The simulation is done by using Synopsys HSPICE tool with 90nm and 32 nm CMOS technologies and whereas for CNTFET 32 nm CNTFET model is chosen. The results show that the performances of the CNTFET based logics are superior compared to other logic families at different CMOS technology nodes.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121245805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Comparison of Linearity Performance of InAs Based DG-MOSFETs with Gate Stack, SiO2 and HfO2 栅极堆、SiO2和HfO2的InAs基dg - mosfet线性性能比较
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770386
S. Swain, Sarosij Adak, S. Biswal, Biswajit Baral, S. Parija
{"title":"Comparison of Linearity Performance of InAs Based DG-MOSFETs with Gate Stack, SiO2 and HfO2","authors":"S. Swain, Sarosij Adak, S. Biswal, Biswajit Baral, S. Parija","doi":"10.1109/EDKCON.2018.8770386","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770386","url":null,"abstract":"This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"25 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133880046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of MEMS Temperature Sensor Using Molybdenum Material for Enhancing Its Performance 基于钼材料的MEMS温度传感器设计
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770398
S. Manikandan, V. R. Prakash, M. Saravanan, P. Diderot
{"title":"Design of MEMS Temperature Sensor Using Molybdenum Material for Enhancing Its Performance","authors":"S. Manikandan, V. R. Prakash, M. Saravanan, P. Diderot","doi":"10.1109/EDKCON.2018.8770398","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770398","url":null,"abstract":"In this paper, a design of a Micro Electro Mechanical System (MEMS)based temperature sensor using molybdenum is discussed. The optimization of the shape and dimensions has been done to improve its performance characteristics. The designed MEMS Sensors will have length and width of 6.5mm⨯4mm respectively to provide better results. The optimized design was converted into a device through fabrication and it was tested. Such temperature sensor results in very high accuracy with excellent noise immunity and small in size. A novel COSMOL multiphysics approach has been employed for designing the sensor to enhance its characteristics.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115836378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Copyright 版权
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/edkcon.2018.8770483
{"title":"Copyright","authors":"","doi":"10.1109/edkcon.2018.8770483","DOIUrl":"https://doi.org/10.1109/edkcon.2018.8770483","url":null,"abstract":"","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115266066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RingFET Architecture for High Frequency Applications: TCAD based Assessment 高频应用的RingFET架构:基于TCAD的评估
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770410
V. Kumari, M. Saxena, Mridula Gupta
{"title":"RingFET Architecture for High Frequency Applications: TCAD based Assessment","authors":"V. Kumari, M. Saxena, Mridula Gupta","doi":"10.1109/EDKCON.2018.8770410","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770410","url":null,"abstract":"In this work, TCAD based investigation of RingFET architecture has been carried for high frequency applications. ATLAS TCAD device simulation software has been used to exploits the RingFET performance and are also compared with the equivalent bulk MOSFET. Parameters such as: cut-off frequency, max. transducer power gain, Stern Stability factor, Unilateral power gain, scattering parameters and parasitic capacitance (i.e. Cgs and Cgd)are evaluated. Maximum cut-off frequency of 3.7 THz has been achieved with RingFET (having drain outside)architecture at 32nm channel length. With the reduction in substrate doping, gate workfunction and enhancement in gate voltage, superior cut-off frequency can be achieved. Due to asymmetric nature of RingFET architecture, lower cut-off frequency is observed for drain inside case (i.e. 3.4 THz)compared to drain outside case of RingFET. Also, the change in gate to source capacitance Cgs with substrate doping is higher in comparison to gate to drain capacitance Cgd in RingFET.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123226986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Quantum Cost Optimized Design of Reversible 2's Complement Code Converter 可逆2补码转换器的量子成本优化设计
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770220
H. Maity, A. Biswas, Anita Pal, A. Bhattacharjee
{"title":"Quantum Cost Optimized Design of Reversible 2's Complement Code Converter","authors":"H. Maity, A. Biswas, Anita Pal, A. Bhattacharjee","doi":"10.1109/EDKCON.2018.8770220","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770220","url":null,"abstract":"In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123530029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power and Delay Analysis of Junction-Less Double Gate CMOS Inverter in Near and Sub-Threshold Regime 近阈值和亚阈值状态下无结双栅CMOS逆变器的功率和时延分析
2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI: 10.1109/EDKCON.2018.8770468
Dipanjan Sen, Bijit Banik, Swarnil Roy
{"title":"Power and Delay Analysis of Junction-Less Double Gate CMOS Inverter in Near and Sub-Threshold Regime","authors":"Dipanjan Sen, Bijit Banik, Swarnil Roy","doi":"10.1109/EDKCON.2018.8770468","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770468","url":null,"abstract":"In this paper, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. D.C performances like power and delay of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Impact of supply voltage and the temperature on the power and delay of the Inverter circuits have been detailed here. Extensive simulations have been done using SILVACO ATLAS to validate the proposed models. Besides, optimum, supply voltage has been proposed to enhance the efficiency at low supply voltage.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122553595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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